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to our customers, old company name in catalogs and other documents on april 1 st , 2010, nec electronics corporation merged with renesas technology corporation, and renesas electronics corporation took over all the business of both companies. therefore, although the old company name remains in this document, it is a valid renesas electronics document. we appreciate your understanding. renesas electronics website: http://www.renesas.com april 1 st , 2010 renesas electronics corporation issued by: renesas electronics corporation ( http://www.renesas.com ) send any inquiries to http://www.renesas.com/inquiry .
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h8/3664 group hardware manual 16 users manual rev.6.00 2006.03 renesas 16-bit single-chip microcomputer h8 family/h8/300h tiny series h8/3664n HD64N3664 h8/3664f hd64f3664 h8/3664 hd6433664 h8/3663 hd6433663 h8/3662 hd6433662 h8/3661 hd6433661 h8/3660 hd6433660
rev. 6.00 mar. 24, 2006 page ii of xxviii
rev. 6.00 mar. 24, 2006 page iii of xxviii 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas technology corp. or a third party. 2. renesas technology corp. assumes no responsibility for any damage, or infringement of any third- party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by renesas technology corp. without notice due to product improvements or other reasons. it is therefore recommended that customers contact renesas technology corp. or an authorized renesas technology corp. product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by renesas technology corp. by various means, including the renesas technology corp. semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact renesas technology corp. or an authorized renesas technology corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technology corp. is necessary to reprint or reproduce in whole or in part these materials. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. 8. please contact renesas technology corp. for further details on these materials or the products contained therein. 1. renesas technology corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. keep safety first in your circuit designs! notes regarding these materials
rev. 6.00 mar. 24, 2006 page iv of xxviii general precautions on handling of product 1. treatment of nc pins note: do not connect anything to the nc pins. the nc (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. if something is connected to the nc pins, the operation of the lsi is not guaranteed. 2. treatment of unused input pins note: fix all unused input pins to high or low level. generally, the input pins of cmos products are high-impedance input pins. if unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a pass- through current flows internally, and a malfunction may occur. 3. processing before initialization note: when power is first supplied, the product's state is undefined. the states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pi n. during the period where the states are undefined, the register settings and the output state of each pin are also undefined. design your system so that it does not malfunction because of processing while it is in this undefined state. for those products which have a reset function, reset the lsi immediately after the power supply has been turned on. 4. prohibition of access to undefined or reserved addresses note: access to undefined or reserved addresses is prohibited. the undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresse s. do not access these registers; the system's operation is not guaranteed if they are accessed.
rev. 6.00 mar. 24, 2006 page v of xxviii configuration of this manual this manual comprises the following items: 1. general precautions on handling of product 2. configuration of this manual 3. preface 4. contents 5. overview 6. description of functional modules ? cpu and system-control modules ? on-chip peripheral modules the configuration of the functional description of each module differs according to the module. however, the generic style includes the following items: i) feature ii) input/output pin iii) register description iv) operation v) usage note when designing an application system that includes this lsi, take notes into account. each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. list of registers 8. electrical characteristics 9. appendix 10. main revisions and additions in this edition (only for revised versions) the list of revisions is a summary of points that have been revised or added to earlier versions. this does not include all of the revised contents . for details, see the actual locations in this manual. 11. index
rev. 6.00 mar. 24, 2006 page vi of xxviii preface the h8/3664 group are single-chip microcomputers made up of the high-speed h8/300h cpu employing renesas technology original architectur e as their cores, and th e peripheral functions required to configure a system. the h8/300h cpu ha s an instruction set that is compatible with the h8/300 cpu. target users: this manual was written for users who will be using the h8/3664 group in the design of application systems. target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. objective: this manual was written to explain the hardware functions and electrical characteristics of th e h8/3664 group to the target users. refer to the h8/300h series software ma nual for a detailed description of the instruction set. notes on reading this manual: ? in order to understand the overall functions of the chip read the manual according to the contents. this manual can be roughly categorized into parts on the cpu, system control functions, periph eral functions and elect rical characteristics. ? in order to understand the details of the cpu's functions read the h8/300h series software manual. ? in order to understand the details of a register when its name is known read the index that is the final part of the manual to find the page number of the entry on the register. the addresses, bits, and initial values of the registers are summarized in section 19, list of registers. example: bit order: the msb is on the left and the lsb is on the right. notes: when using the on-chip emulator (e7, e8) for h8/3664 program development and debugging, the following restrictions must be noted. 1. the nmi pin is reserved for the e7 or e8, and cannot be used. 2. pins p85, p86, and p87 cannot be used. in order to use these pins, additional hardware must be provided on the user board. 3. area h'7000 to h'7fff is used by the e7 or e8, and is not available to the user. 4. area h'f780 to h'fb7f must on no account be accessed.
rev. 6.00 mar. 24, 2006 page vii of xxviii 5. when the e7 or e8 is used, address breaks can be set as either available to the user or for use by the e7 or e8. if address breaks are set as being used by the e7 or e8, the address break control registers must not be accessed. 6. when the e7 or e8 is used, nmi is an input/output pin (open-drain in output mode), p85 and p87 are input pins, and p86 is an output pin. related manuals: the latest versions of all related manuals are available from our web site. please ensure you have the latest versions of all documents you require. http://www.renesas.com/ h8/3664 group manuals: document title document no. h8/3664 group hardware manual this manual h8/300h series software manual rej09b0213 user's manuals for development tools: document title document no. h8s, h8/300 series c/c++ compiler, assembler, optimizing linkage editor user's manual rej10b0058 h8s, h8/300 series simulator/debugger user's manual rej10b0211 h8s, h8/300 series high-performance embedded workshop 3 tutorial rej10b0024 h8s, h8/300 series high-performance embedded workshop 3 user's manual rej10b0026 application notes: document title document no. h8s, h8/300 series c/c++ compiler package application note rej05b0464 single power supply f-ztat tm on-board programming rej05b0520
rev. 6.00 mar. 24, 2006 page viii of xxviii
rev. 6.00 mar. 24, 2006 page ix of xxviii contents section 1 overview................................................................................................1 1.1 features....................................................................................................................... .......... 1 1.2 internal bloc k diagram......................................................................................................... 3 1.3 pin arrangement ................................................................................................................ ... 5 1.4 pin functions .................................................................................................................. ...... 9 section 2 cpu......................................................................................................13 2.1 address space and memory map ....................................................................................... 14 2.2 register conf iguratio n........................................................................................................ 1 7 2.2.1 general registers................................................................................................ 18 2.2.2 program counter (pc) ........................................................................................ 19 2.2.3 condition-code re gister (ccr)......................................................................... 19 2.3 data formats................................................................................................................... .... 21 2.3.1 general register data formats ........................................................................... 21 2.3.2 memory data formats ........................................................................................ 23 2.4 instruction set ................................................................................................................ ..... 24 2.4.1 table of instructions cl assified by function ...................................................... 24 2.4.2 basic instructio n formats ................................................................................... 34 2.5 addressing modes and effec tive address ca lculation....................................................... 35 2.5.1 addressing modes .............................................................................................. 35 2.5.2 effective address calculation ............................................................................ 39 2.6 basic bus cycle ................................................................................................................ .. 41 2.6.1 access to on-chip me mory (ram, rom)........................................................ 41 2.6.2 on-chip peripheral modules .............................................................................. 42 2.7 cpu states ..................................................................................................................... ..... 43 2.8 usage notes .................................................................................................................... .... 44 2.8.1 notes on data acce ss to empty areas ............................................................... 44 2.8.2 eepmov instru ction.......................................................................................... 44 2.8.3 bit manipulation instruction............................................................................... 45 section 3 exception handling .............................................................................51 3.1 exception sources and vector address .............................................................................. 51 3.2 register de scriptions.......................................................................................................... 53 3.2.1 interrupt edge select register 1 (iegr1) .......................................................... 53 3.2.2 interrupt edge select register 2 (iegr2) .......................................................... 54 3.2.3 interrupt enable regi ster 1 (ienr1) .................................................................. 55
rev. 6.00 mar. 24, 2006 page x of xxviii 3.2.4 interrupt flag register 1 (irr1)......................................................................... 56 3.2.5 wakeup interrupt flag register (iwpr) ............................................................ 57 3.3 reset exceptio n handling .................................................................................................. 59 3.4 interrupt exception handling ............................................................................................. 59 3.4.1 external interrupts .............................................................................................. 59 3.4.2 internal interrupts ............................................................................................... 61 3.4.3 interrupt handling sequence ..................................................................... 61 3.4.4 interrupt response time..................................................................................... 62 3.5 usage notes .................................................................................................................... .... 64 3.5.1 interrupts after reset........................................................................................... 64 3.5.2 notes on stack area use .................................................................................... 64 3.5.3 notes on rewriting port mode registers ........................................................... 64 section 4 address break ..................................................................................... 67 4.1 register de scriptions.......................................................................................................... 68 4.1.1 address break control register (a brkcr) ..................................................... 68 4.1.2 address break status register (a brksr) ........................................................ 70 4.1.3 break address register s (barh, barl).......................................................... 70 4.1.4 break data register s (bdrh, bdrl) ............................................................... 70 4.2 operation ...................................................................................................................... ...... 71 4.3 usage notes .................................................................................................................... .... 73 section 5 clock pulse generators ....................................................................... 77 5.1 system clock generator ..................................................................................................... 78 5.1.1 connecting crysta l resona tor ............................................................................ 78 5.1.2 connecting cerami c resonator .......................................................................... 79 5.1.3 external clock input me thod.............................................................................. 79 5.2 subclock generator ............................................................................................................ 8 0 5.2.1 connecting 32.768-khz cr ystal resonator ........................................................ 80 5.2.2 pin connection when no t using subclock......................................................... 81 5.3 prescalers ..................................................................................................................... ....... 81 5.3.1 prescaler s .......................................................................................................... 81 5.3.2 prescaler w......................................................................................................... 81 5.4 usage notes .................................................................................................................... .... 82 5.4.1 note on resonators............................................................................................. 82 5.4.2 notes on board design ....................................................................................... 82 section 6 power-down modes............................................................................ 83 6.1 register de scriptions.......................................................................................................... 84 6.1.1 system control regi ster 1 (syscr1) ................................................................ 84
rev. 6.00 mar. 24, 2006 page xi of xxviii 6.1.2 system control regi ster 2 (syscr2) ................................................................ 86 6.1.3 module standby control register 1 (mstcr1) ................................................ 87 6.2 mode transitions and states of lsi.................................................................................... 88 6.2.1 sleep mode ......................................................................................................... 91 6.2.2 standby mode ..................................................................................................... 91 6.2.3 subsleep mode.................................................................................................... 92 6.2.4 subactive mode .................................................................................................. 92 6.3 operating frequency in active mode................................................................................. 93 6.4 direct tr ansition .............................................................................................................. ... 93 6.4.1 direct transition from active mode to suba ctive mode.................................... 93 6.4.2 direct transition from subact ive mode to ac tive mode.................................... 94 6.5 module standby function................................................................................................... 94 6.6 usage note..................................................................................................................... ..... 94 section 7 rom ....................................................................................................95 7.1 block confi guratio n ........................................................................................................... 9 6 7.2 register de scriptions.......................................................................................................... 97 7.2.1 flash memory control re gister 1 (flmcr1).................................................... 97 7.2.2 flash memory control re gister 2 (flmcr2).................................................... 98 7.2.3 erase block register 1 (ebr1) .......................................................................... 99 7.2.4 flash memory power contro l register (flpwcr) ........................................... 99 7.2.5 flash memory enable register (f enr) ........................................................... 100 7.3 on-board programmi ng modes........................................................................................ 100 7.3.1 boot mode ........................................................................................................ 101 7.3.2 programming/erasing in user program mode.................................................. 103 7.4 flash memory progra mming/erasing............................................................................... 104 7.4.1 program/progra m-verify .................................................................................. 104 7.4.2 erase/erase- verify............................................................................................ 107 7.4.3 interrupt handling when progra mming/erasing flash memory....................... 107 7.5 program/erase pr otection ................................................................................................. 109 7.5.1 hardware protection ......................................................................................... 109 7.5.2 software protection........................................................................................... 109 7.5.3 error protection................................................................................................. 109 7.6 programmer mode ............................................................................................................ 110 7.7 power-down states fo r flash memory............................................................................. 110 section 8 ram ..................................................................................................113 section 9 i/o ports .............................................................................................115 9.1 port 1......................................................................................................................... ........ 115
rev. 6.00 mar. 24, 2006 page xii of xxviii 9.1.1 port mode regist er 1 (pmr1) .......................................................................... 116 9.1.2 port control regist er 1 (pcr1) ........................................................................ 117 9.1.3 port data regist er 1 (pdr1) ............................................................................ 118 9.1.4 port pull-up control re gister 1 (pucr1)........................................................ 118 9.1.5 pin functions .................................................................................................... 119 9.2 port 2......................................................................................................................... ........ 121 9.2.1 port control regist er 2 (pcr2) ........................................................................ 121 9.2.2 port data regist er 2 (pdr2) ............................................................................ 122 9.2.3 pin functions .................................................................................................... 122 9.3 port 5......................................................................................................................... ........ 124 9.3.1 port mode regist er 5 (pmr5) .......................................................................... 125 9.3.2 port control regist er 5 (pcr5) ........................................................................ 126 9.3.3 port data regist er 5 (pdr5) ............................................................................ 127 9.3.4 port pull-up control re gister 5 (pucr5)........................................................ 127 9.3.5 pin functions .................................................................................................... 128 9.4 port 7......................................................................................................................... ........ 130 9.4.1 port control regist er 7 (pcr7) ........................................................................ 131 9.4.2 port data regist er 7 (pdr7) ............................................................................ 131 9.4.3 pin functions .................................................................................................... 132 9.5 port 8......................................................................................................................... ........ 133 9.5.1 port control regist er 8 (pcr8) ........................................................................ 134 9.5.2 port data regist er 8 (pdr8) ............................................................................ 134 9.5.3 pin functions .................................................................................................... 135 9.6 port b......................................................................................................................... ....... 138 9.6.1 port data regist er b (pdrb) ........................................................................... 138 section 10 timer a ........................................................................................... 139 10.1 features....................................................................................................................... ...... 139 10.2 input/output pins.............................................................................................................. 140 10.3 register desc riptions........................................................................................................ 14 1 10.3.1 timer mode regist er a (tma)........................................................................ 141 10.3.2 timer counter a (tca) ................................................................................... 142 10.4 operation ...................................................................................................................... .... 143 10.4.1 interval timer operation .................................................................................. 143 10.4.2 clock time base operatio n.............................................................................. 143 10.4.3 clock outp ut..................................................................................................... 143 10.5 usage note ..................................................................................................................... .. 144 section 11 timer v ........................................................................................... 145 11.1 features....................................................................................................................... ...... 145
rev. 6.00 mar. 24, 2006 page xiii of xxviii 11.2 input/output pins.............................................................................................................. 147 11.3 register desc riptions........................................................................................................ 14 7 11.3.1 timer counter v (tcntv) .............................................................................. 147 11.3.2 time constant registers a and b (tcora, tcorb) .................................... 148 11.3.3 timer control regist er v0 (tcrv0) ............................................................... 148 11.3.4 timer control/status re gister v (tcsrv) ...................................................... 150 11.3.5 timer control regist er v1 (tcrv1) ............................................................... 151 11.4 operation ...................................................................................................................... .... 152 11.4.1 timer v operation............................................................................................ 152 11.5 timer v applicati on examples ........................................................................................ 155 11.5.1 pulse output with arb itrary duty cycle........................................................... 155 11.5.2 pulse output with arbitrary pulse wi dth and delay from trgv input .......... 156 11.6 usage notes .................................................................................................................... .. 157 section 12 timer w ...........................................................................................159 12.1 features....................................................................................................................... ...... 159 12.2 input/output pins.............................................................................................................. 162 12.3 register desc riptions........................................................................................................ 16 2 12.3.1 timer mode regist er w (tmrw) ................................................................... 163 12.3.2 timer control regist er w (tcrw) ................................................................. 164 12.3.3 timer interrupt enable re gister w (tierw) .................................................. 165 12.3.4 timer status regist er w (tsrw) .................................................................... 166 12.3.5 timer i/o control regi ster 0 (tio r0) ............................................................. 167 12.3.6 timer i/o control regi ster 1 (tio r1) ............................................................. 169 12.3.7 timer counter (tcnt)..................................................................................... 170 12.3.8 general registers a to d (gra to grd)......................................................... 171 12.4 operation ...................................................................................................................... .... 172 12.4.1 normal operation ............................................................................................. 172 12.4.2 pwm opera tion................................................................................................ 176 12.5 operation timing.............................................................................................................. 1 81 12.5.1 tcnt count timing ........................................................................................ 181 12.5.2 output compare output timing ....................................................................... 182 12.5.3 input capture timing........................................................................................ 183 12.5.4 timing of counter clearin g by compare match .............................................. 183 12.5.5 buffer operatio n timing .................................................................................. 184 12.5.6 timing of imfa to imfd flag setting at comp are match.............................. 185 12.5.7 timing of imfa to imfd se tting at input capture ......................................... 186 12.5.8 timing of status flag clearing......................................................................... 186 12.6 usage notes .................................................................................................................... .. 187
rev. 6.00 mar. 24, 2006 page xiv of xxviii section 13 watchdog timer.............................................................................. 191 13.1 features....................................................................................................................... ...... 191 13.2 register desc riptions........................................................................................................ 19 1 13.2.1 timer control/status regi ster wd (tcsrwd) .............................................. 192 13.2.2 timer counter wd (tcwd)............................................................................ 193 13.2.3 timer mode register wd (tmwd) ................................................................ 194 13.3 operation ...................................................................................................................... .... 195 section 14 serial communication interface 3 ( s ci3 ) ...................................... . 197 14.1 features....................................................................................................................... ...... 197 14.2 input/output pins.............................................................................................................. 198 14.3 register desc riptions........................................................................................................ 19 9 14.3.1 receive shift regi ster (rsr) ........................................................................... 199 14.3.2 receive data regi ster (rdr)........................................................................... 199 14.3.3 transmit shift regi ster (tsr) .......................................................................... 199 14.3.4 transmit data regi ster (tdr).......................................................................... 200 14.3.5 serial mode regi ster (smr) ............................................................................ 200 14.3.6 serial control regi ster 3 (scr3) ..................................................................... 201 14.3.7 serial status regi ster (ssr) ............................................................................. 203 14.3.8 bit rate regist er (brr) ................................................................................... 205 14.4 operation in asynch ronous mode .................................................................................... 210 14.4.1 clock................................................................................................................. 210 14.4.2 sci3 initiali zation............................................................................................. 211 14.4.3 data transmission ............................................................................................ 212 14.4.4 serial data reception ....................................................................................... 214 14.5 operation in clocked synchronous mode ........................................................................ 218 14.5.1 clock................................................................................................................. 218 14.5.2 sci3 initiali zation............................................................................................. 218 14.5.3 serial data tr ansmission .................................................................................. 219 14.5.4 serial data reception (clock ed synchronous mode) ...................................... 221 14.5.5 simultaneous serial data tran smission and reception.................................... 223 14.6 multiprocessor communi cation func tion ........................................................................ 224 14.6.1 multiprocessor serial da ta transmission ......................................................... 226 14.6.2 multiprocessor serial data reception .............................................................. 227 14.7 interrupts..................................................................................................................... ...... 230 14.8 usage notes .................................................................................................................... .. 230 14.8.1 break detection an d processing ....................................................................... 230 14.8.2 mark state and br eak sending ......................................................................... 231 14.8.3 receive error flags and transmit operations (clocked synchronous mode only) ................................................................. 231
rev. 6.00 mar. 24, 2006 page xv of xxviii 14.8.4 receive data sampling timing and reception margin in asynchronous mode ..................................................................................... 231 section 15 i 2 c bus interface (iic) .....................................................................233 15.1 features....................................................................................................................... ...... 233 15.2 input/output pins.............................................................................................................. 235 15.3 register desc riptions........................................................................................................ 23 6 15.3.1 i 2 c bus data regist er (icdr) .......................................................................... 236 15.3.2 slave address regi ster (sar).......................................................................... 238 15.3.3 second slave address register (sarx) .......................................................... 238 15.3.4 i 2 c bus mode regist er (icmr)........................................................................ 239 15.3.5 i 2 c bus control regi ster (icc r)...................................................................... 242 15.3.6 i 2 c bus status regi ster (icsr)......................................................................... 245 15.3.7 timer serial control register (t scr) ............................................................. 248 15.4 operation ...................................................................................................................... .... 249 15.4.1 i 2 c bus data format ......................................................................................... 249 15.4.2 master transmit operation ............................................................................... 251 15.4.3 master receive operatio n................................................................................. 253 15.4.4 slave receive op eration................................................................................... 255 15.4.5 slave transmit op eration ................................................................................. 258 15.4.6 clock synchronous se rial format .................................................................... 259 15.4.7 iric setting timing an d scl control ............................................................. 260 15.4.8 noise canceler.................................................................................................. 261 15.4.9 sample flow charts............................................................................................ 262 15.5 usage notes .................................................................................................................... .. 266 section 16 a/d converter..................................................................................275 16.1 features....................................................................................................................... ...... 275 16.2 input/output pins.............................................................................................................. 277 16.3 register desc ription ......................................................................................................... 27 8 16.3.1 a/d data registers a to d (addra to addrd) .......................................... 278 16.3.2 a/d control/status regi ster (adcsr) ............................................................ 279 16.3.3 a/d control regist er (adcr) ......................................................................... 280 16.4 operation ...................................................................................................................... .... 281 16.4.1 single mode...................................................................................................... 281 16.4.2 scan mode ........................................................................................................ 281 16.4.3 input sampling and a/d conversion time ...................................................... 282 16.4.4 external trigger input timi ng.......................................................................... 283 16.5 a/d conversion accura cy definitions ............................................................................. 284 16.6 usage notes .................................................................................................................... .. 286
rev. 6.00 mar. 24, 2006 page xvi of xxviii 16.6.1 permissible signal s ource impedance .............................................................. 286 16.6.2 influences on abso lute accuracy ..................................................................... 286 section 17 eeprom......................................................................................... 287 17.1 features....................................................................................................................... ...... 287 17.2 input/output pins.............................................................................................................. 289 17.3 register desc ription ......................................................................................................... 28 9 17.3.1 eeprom key regist er (ekr)......................................................................... 289 17.4 operation ...................................................................................................................... .... 290 17.4.1 eeprom inte rface........................................................................................... 290 17.4.2 bus format and timing .................................................................................... 290 17.4.3 start condi tion.................................................................................................. 291 17.4.4 stop cond ition .................................................................................................. 291 17.4.5 acknowledge .................................................................................................... 291 17.4.6 slave addressing .............................................................................................. 292 17.4.7 write operations............................................................................................... 293 17.4.8 acknowledge polling........................................................................................ 294 17.4.9 read operation ................................................................................................. 295 17.5 usage notes .................................................................................................................... .. 297 17.5.1 data protection at v cc on/off........................................................................... 297 17.5.2 write/erase en durance ..................................................................................... 297 17.5.3 noise suppress ion time ................................................................................... 298 section 18 power supply circuit ...................................................................... 299 18.1 when using internal power su pply step-down circuit .................................................. 299 18.2 when not using internal power supply step-dow n circuit ........................................... 300 section 19 list of registers............................................................................... 301 19.1 register addresses (a ddress order)................................................................................. 302 19.2 register bits .................................................................................................................. ... 305 19.3 register states in ea ch operating mode .......................................................................... 308 section 20 electrical characteristics ................................................................. 311 20.1 absolute maximum ratings ............................................................................................. 311 20.2 electrical characteristics (f-ztat? versio n, f-ztat? version with eeprom) ..... 311 20.2.1 power supply voltage an d operating ranges .................................................. 311 20.2.2 dc character istics ............................................................................................ 314 20.2.3 ac character istics ............................................................................................ 320 20.2.4 a/d converter char acteristic s.......................................................................... 324 20.2.5 watchdog timer ch aracteristic s....................................................................... 325
rev. 6.00 mar. 24, 2006 page xvii of xxviii 20.2.6 memory characte ristics .................................................................................... 326 20.2.7 eeprom character istics.................................................................................. 328 20.3 electrical characteristics (mask rom version) .............................................................. 329 20.3.1 power supply voltage an d operating ranges .................................................. 329 20.3.2 dc character istics ............................................................................................ 331 20.3.3 ac character istics ............................................................................................ 337 20.3.4 a/d converter char acteristic s .......................................................................... 341 20.3.5 watchdog timer ch aracteristic s....................................................................... 342 20.4 operation timing.............................................................................................................. 3 43 20.5 output load condition ..................................................................................................... 346 appendix a instruction set ...............................................................................347 a.1 instruction list............................................................................................................... ... 347 a.2 operation code map......................................................................................................... 362 a.3 number of execu tion stat es ............................................................................................. 365 a.4 combinations of instructions and addressing modes ...................................................... 376 appendix b i/o port block diagrams ...............................................................377 b.1 i/o port block................................................................................................................. .. 377 b.2 port states in each operating st ate .................................................................................. 394 appendix c product code lineup.....................................................................395 appendix d package dimensions .....................................................................397 appendix e eeprom stacked-stru cture cross-sectional view .....................401 main revisions and additions in this edition .....................................................403 index ....................................................................................................................409
rev. 6.00 mar. 24, 2006 page xviii of xxviii
rev. 6.00 mar. 24, 2006 page xix of xxviii figures section 1 overview figure 1.1 internal block diagram of h8/3664 of f-ztat tm and mask-rom versions ............. 3 figure 1.2 internal block diagram of h8/3664n of f-ztat tm version with eeprom ............. 4 figure 1.3 pin arrangement of h8/3664 of f-ztat tm and mask-rom versions (fp-64e, fp-64a)................................................................................................... ...... 5 figure 1.4 pin arrangement of h8/3664 of f-ztat tm and mask-rom versions (fp-48f, fp-48b) ................................................................................................... ...... 6 figure 1.5 pin arrangement of h8/3664 of f-ztat tm and mask-rom versions (ds-42s) ........................................................................................................... ............ 7 figure 1.6 pin arrangement of h8/3664n of f-ztat tm version with eeprom (fp-64e) ........................................................................................................... ............ 8 section 2 cpu figure 2.1 memory map (1) .................................................................................................... ..... 14 figure 2.1 memory map (2) .................................................................................................... ..... 15 figure 2.1 memory map (3) .................................................................................................... ..... 16 figure 2.2 cpu regi sters ..................................................................................................... ........ 17 figure 2.3 usage of general registers ........................................................................................ .18 figure 2.4 relationship between stack pointer an d stack area ................................................... 19 figure 2.5 general regi ster data formats (1).............................................................................. 21 figure 2.5 general regi ster data formats (2).............................................................................. 22 figure 2.6 memo ry data formats............................................................................................... .. 23 figure 2.7 inst ruction formats............................................................................................... ....... 34 figure 2.8 branch address specifi cation in memory indirect mode ........................................... 38 figure 2.9 on-chip memory acces s cycle.................................................................................. 41 figure 2.10 on-chip peripheral mo dule access cycle (3 -state access)..................................... 42 figure 2.11 cp u operation states............................................................................................. ... 43 figure 2.12 state tran siti ons ................................................................................................ ........ 44 figure 2.13 example of timer configuration with two registers allocated to same address ..................................................................................................... ...... 45 section 3 exception handling figure 3.1 reset se quence.................................................................................................... ........ 60 figure 3.2 stack status after exceptio n handling ........................................................................ 62 figure 3.3 interrupt sequence................................................................................................ ....... 63 figure 3.4 port mode regi ster setting and interrupt reques t flag clearing procedure .............. 65 section 4 address break figure 4.1 block diag ram of address break................................................................................ 67
rev. 6.00 mar. 24, 2006 page xx of xxviii figure 4.2 address break inte rrupt operation example (1)......................................................... 71 figure 4.2 address break inte rrupt operation example (2)......................................................... 72 figure 4.3 operation when condition is not satisfied in bran ch instru ction ............................... 73 figure 4.4 operation when another interrupt is accepted at address break setting in struction ............................................................................... 74 figure 4.5 operation when the instruction set is not executed and does not branch due to conditions no t being sa tisfied ........................................ 75 section 5 clock pulse generators figure 5.1 block diagram of clock pulse generators.................................................................. 77 figure 5.2 block diagram of system clock generator ................................................................ 78 figure 5.3 typical connect ion to crystal resonator.................................................................... 78 figure 5.4 equivalent circ uit of crystal resonator...................................................................... 78 figure 5.5 typical connect ion to ceramic resonator.................................................................. 79 figure 5.6 example of external clock input ................................................................................ 79 figure 5.7 block diagram of subclock generator ....................................................................... 80 figure 5.8 typical connection to 32.768-khz crysta l resonator................................................ 80 figure 5.9 equivalent circuit of 32.768-khz crys tal resona tor.................................................. 80 figure 5.10 pin connectio n when not using subclock ................................................................ 81 figure 5.11 example of incorrect board design .......................................................................... 82 section 6 power-down modes figure 6.1 mode transition diagram ........................................................................................... 88 section 7 rom figure 7.1 flash memory block config uration............................................................................ 96 figure 7.2 programming/erasing flowch art example in user program mode.......................... 103 figure 7.3 program/prog ram-verify fl owchart ......................................................................... 105 figure 7.4 erase/eras e-verify flowchart ................................................................................... 108 section 9 i/o ports figure 9.1 port 1 pin config uration.......................................................................................... .. 115 figure 9.2 port 2 pin config uration.......................................................................................... .. 121 figure 9.3 port 5 pin config uration.......................................................................................... .. 124 figure 9.4 port 7 pin config uration.......................................................................................... .. 130 figure 9.5 port 8 pin config uration.......................................................................................... .. 133 figure 9.6 port b pin config uration.......................................................................................... .138 section 10 timer a figure 10.1 block di agram of timer a ..................................................................................... 140 section 11 timer v figure 11.1 block di agram of timer v ..................................................................................... 146
rev. 6.00 mar. 24, 2006 page xxi of xxviii figure 11.2 increment timi ng with intern al clock .................................................................... 153 figure 11.3 increment timi ng with extern al clock ................................................................... 153 figure 11.4 ovf set timing ................................................................................................... ... 153 figure 11.5 cmfa an d cmfb set timing ................................................................................ 154 figure 11.6 tmov output timing ............................................................................................ 154 figure 11.7 clear timi ng by compare match............................................................................ 154 figure 11.8 clear ti ming by tmriv input ............................................................................... 155 figure 11.9 pulse output example ............................................................................................. 155 figure 11.10 example of pulse outp ut synchronized to trgv input....................................... 156 figure 11.11 contention betw een tcntv write and clear ...................................................... 157 figure 11.12 contention between tcora write and co mpare match ..................................... 158 figure 11.13 internal clock sw itching and tcntv operation ................................................. 158 section 12 timer w figure 12.1 timer w block diagram ......................................................................................... 161 figure 12.2 free-runnin g counter operation ............................................................................ 172 figure 12.3 periodic counter operation..................................................................................... 17 3 figure 12.4 0 and 1 output example (toa = 0, tob = 1)........................................................ 173 figure 12.5 toggle output example (toa = 0, tob = 1) ........................................................ 174 figure 12.6 toggle output example (toa = 0, tob = 1) ........................................................ 174 figure 12.7 input capt ure operating example........................................................................... 175 figure 12.8 buffer operatio n example (input capture)............................................................. 176 figure 12.9 pwm mo de example (1) ........................................................................................ 177 figure 12.10 pwm m ode example (2) ...................................................................................... 177 figure 12.11 buffer operatio n example (outpu t compare) ...................................................... 178 figure 12.12 pwm mode example (tob, toc, and to d = 0: initial output valu es are set to 0)............................... 179 figure 12.13 pwm mode example (tob, toc, and to d = 1: initial output valu es are set to 1)............................... 180 figure 12.14 count timing fo r internal cloc k source ............................................................... 181 figure 12.15 count timing fo r external cloc k source.............................................................. 181 figure 12.16 output co mpare output timing ........................................................................... 182 figure 12.17 input capt ure input signa l timing........................................................................ 183 figure 12.18 timing of counte r clearing by comp are matc h................................................... 183 figure 12.19 buffer operat ion timing (compa re match).......................................................... 184 figure 12.20 buffer operat ion timing (input capture) ............................................................. 184 figure 12.21 timing of imfa to im fd flag setting at compare match .................................. 185 figure 12.22 timing of imfa to im fd flag setting at input capture...................................... 186 figure 12.23 timing of stat us flag clearing by cpu................................................................ 186 figure 12.24 contention betw een tcnt write and clear ......................................................... 187 figure 12.25 internal clock sw itching and tcnt operation.................................................... 188
rev. 6.00 mar. 24, 2006 page xxii of xxviii figure 12.26 when compare match and bit manipulation instruction to tcrw occur at the same timing .................................................................................... 189 section 13 watchdog timer figure 13.1 block diagra m of watchdog timer ........................................................................ 191 figure 13.2 watchdog ti mer operation example...................................................................... 195 section 14 serial commu nication interface 3 (sci3) figure 14.1 bloc k diagram of sci3........................................................................................... 1 98 figure 14.2 data format in asynchronous co mmunication ...................................................... 210 figure 14.3 relationship between output clock and transfer data phase (asynchronous mode) (examp le with 8-bit data, parity, two stop bits) ............ 210 figure 14.4 sample sci3 initialization fl owchart ..................................................................... 211 figure 14.5 example sci3 operation in transmission in asynchronous mode (8-bit data, parity, one stop b it).......................................................................... 212 figure 14.6 sample serial transmi ssion flowchart (async hronous mode) .............................. 213 figure 14.7 example sci3 operatio n in reception in asynchronous mode (8-bit data, parity, one stop b it).......................................................................... 214 figure 14.8 sample serial data recep tion flowchart (asynchronous mode) (1)...................... 216 figure 14.8 sample serial reception data flow chart (2) .......................................................... 217 figure 14.9 data format in cl ocked synchronous communication .......................................... 218 figure 14.10 example of sci3 operation in transmission in clocked synchronous mode...... 219 figure 14.11 sample serial transmission flowchart (clocked sy nchronous mode) ................ 220 figure 14.12 example of sci3 reception operation in clocked synchronous mode............... 221 figure 14.13 sample serial reception fl owchart (clocked sync hronous mo de)...................... 222 figure 14.14 sample flowchart of simultaneous serial transmit and receive operations (c locked synchron ous mode) .............................................................................. 223 figure 14.15 example of communication using multiprocessor format (transmission of data h'aa to recei ving statio n a).......................................... 225 figure 14.16 sample multiprocessor serial transmissi on flowchart ........................................ 226 figure 14.17 sample multiprocessor serial reception fl owchart (1)........................................ 227 figure 14.17 sample multiprocessor serial reception fl owchart (2)........................................ 228 figure 14.18 example of sci3 opera tion in reception using multiprocessor format (example with 8- bit data, multiprocessor b it, one stop bit) ............................. 229 figure 14.19 receive data sampli ng timing in asynchronous mode ...................................... 232 section 15 i 2 c bus interface (iic) figure 15.1 block diagram of i 2 c bus inte rface ....................................................................... 234 figure 15.2 i 2 c bus interface connections (examp le: this lsi as master) .............................. 235 figure 15.3 i 2 c bus data formats (i 2 c bus formats)................................................................ 250 figure 15.4 i 2 c bus timi ng........................................................................................................ 250 figure 15.5 master transmit mode operat ion timing example (mls = wait = 0).............. 252
rev. 6.00 mar. 24, 2006 page xxiii of xxviii figure 15.6 master receive mo de operation timing example (1) (mls = ackb = 0, wait = 1) ............................................................................. 254 figure 15.6 master receive mode operation timing example (2) (mls = ackb = 0, wait = 1) ............................................................................. 255 figure 15.7 example of slave receive mode operation timing (1) (mls = ackb = 0) ....... 256 figure 15.8 example of slave receive mode operation timing (2) (mls = ackb = 0) ....... 257 figure 15.9 example of slave transm it mode operation timi ng (mls = 0) .......................... 259 figure 15.10 i 2 c bus data format (s erial form at) .................................................................... 259 figure 15.11 iric setting timing and scl control.................................................................. 260 figure 15.12 block diag ram of noise canceler......................................................................... 261 figure 15.13 sample flowchar t for master tr ansmit mode....................................................... 262 figure 15.14 sample flowchar t for master r eceive mode ........................................................ 263 figure 15.15 sample flowch art for slave r eceive mode .......................................................... 264 figure 15.16 sample flowchar t for slave tran smit mode......................................................... 265 figure 15.17 flowchart and timing of start condition instruction issuance for retransmission ............................................................................................. ... 270 figure 15.18 iric flag clea r timing on wait operation ....................................................... 271 figure 15.19 notes on icdr reading w ith trs = 1 setting in master mode........................... 272 figure 15.20 notes on icdr writing with trs = 0 setting in slave mode.............................. 273 section 16 a/d converter figure 16.1 block diag ram of a/d c onverter ........................................................................... 276 figure 16.2 a/d conversion timing .......................................................................................... 28 2 figure 16.3 external trigger input timing ................................................................................ 283 figure 16.4 a/d conversion accuracy definitions (1) .............................................................. 285 figure 16.5 a/d conversion accuracy definitions (2) .............................................................. 285 figure 16.6 analog i nput circuit ex ample................................................................................. 286 section 17 eeprom figure 17.1 block diagram of eeprom ................................................................................... 288 figure 17.2 eeprom bus format and bus timing .................................................................. 290 figure 17.3 byte write operation ............................................................................................. .293 figure 17.4 page write operation ............................................................................................. .294 figure 17.5 current ad dress read op eration............................................................................. 295 figure 17.6 random ad dress read operation ........................................................................... 296 figure 17.7 sequential read operation (when current address read is used)............................. 297 section 18 power supply circuit figure 18.1 power supply connection when internal step-down circuit is used .................... 299 figure 18.2 power supply connection when internal step-down circuit is not used ............. 300
rev. 6.00 mar. 24, 2006 page xxiv of xxviii section 20 electrical characteristics figure 20.1 system clock input timing .................................................................................... 343 figure 20.2 res low width timing.......................................................................................... 343 figure 20.3 input timing..................................................................................................... ....... 343 figure 20.4 i 2 c bus interface inpu t/output ti ming ................................................................... 344 figure 20.5 sck3 input clock timing ...................................................................................... 344 figure 20.6 sci3 input/output ti ming in clocked synchronous mode .................................... 345 figure 20.7 eepr om bus timing............................................................................................. 345 figure 20.8 outp ut load circuit .............................................................................................. .. 346 appendix b i/o port block diagrams figure b.1 port 1 block diagra m (p17) ..................................................................................... 377 figure b.2 port 1 block diagram (p16 to p14) .......................................................................... 378 figure b.3 port 1 bloc k diagram (p12, p11) ............................................................................. 379 figure b.4 port 1 block diagra m (p10) ..................................................................................... 380 figure b.5 port 2 block diagra m (p22) ..................................................................................... 381 figure b.6 port 2 block diagra m (p21) ..................................................................................... 382 figure b.7 port 2 block diagra m (p20) ..................................................................................... 383 figure b.8 port 5 bloc k diagram (p57, p56) ............................................................................. 384 figure b.9 port 5 block diagra m (p55) ..................................................................................... 385 figure b.10 port 5 bloc k diagram (p54 to p50) ........................................................................ 386 figure b.11 port 7 block diagram (p76) ................................................................................... 387 figure b.12 port 7 block diagram (p75) ................................................................................... 388 figure b.13 port 7 block diagram (p74) ................................................................................... 389 figure b.14 port 8 bloc k diagram (p87 to p85) ........................................................................ 390 figure b.15 port 8 bloc k diagram (p84 to p81) ........................................................................ 391 figure b.16 port 8 block diagram (p80) ................................................................................... 392 figure b.17 port b bloc k diagram (pb7 to pb0) ...................................................................... 393 appendix d package dimensions figure d.1 fp-64e package dimensions ................................................................................... 397 figure d.2 fp-64a package dimensions ................................................................................... 398 figure d.3 fp-48f package dimensions.................................................................................... 399 figure d.4 fp-48b package dimensions ................................................................................... 400 figure d.5 dp-42s package dimensions ................................................................................... 400 appendix e eeprom stacked-structure cross-sectional view figure e.1 eeprom stacked-st ructure cross-sec tional vi ew ................................................. 401
rev. 6.00 mar. 24, 2006 page xxv of xxviii tables section 1 overview table 1.1 pin functions ............................................................................................................ 9 section 2 cpu table 2.1 operation notation ................................................................................................. 24 table 2.2 data transfer instructions....................................................................................... 25 table 2.3 arithmetic operations instructions (1) ................................................................... 26 table 2.3 arithmetic operations instructions (2) ................................................................... 27 table 2.4 logic operations instructions................................................................................. 28 table 2.5 shift instru ctions..................................................................................................... 28 table 2.6 bit manipulation inst ructions (1)............................................................................ 29 table 2.6 bit manipulation inst ructions (2)............................................................................ 30 table 2.7 branch instructions ................................................................................................. 31 table 2.8 system control instructions.................................................................................... 32 table 2.9 block data transfer instructions ............................................................................ 33 table 2.10 addressing modes .................................................................................................. 35 table 2.11 absolute address access ranges ........................................................................... 37 table 2.12 effective address ca lculation (1)........................................................................... 39 table 2.12 effective address ca lculation (2)........................................................................... 40 section 3 exception handling table 3.1 exception sources and vector address .................................................................. 52 table 3.2 interrupt wa it states ............................................................................................... 62 section 4 address break table 4.1 access and data bus used ..................................................................................... 69 section 5 clock pulse generators table 5.1 crystal resonato r parameters ................................................................................. 79 section 6 power-down modes table 6.1 operating frequency and waiting time................................................................. 85 table 6.2 transition mode after sleep instructio n execution and interrupt handling ........ 89 table 6.3 internal state in ea ch operating mode................................................................... 90 section 7 rom table 7.1 setting programmi ng modes ................................................................................ 100 table 7.2 boot mode operation ........................................................................................... 102 table 7.3 system clock frequencies for which automatic adjustment of lsi bit rate is possible ........................................................................................ 103
rev. 6.00 mar. 24, 2006 page xxvi of xxviii table 7.4 reprogram data com putation table .................................................................... 106 table 7.5 additional-program data computation table ...................................................... 106 table 7.6 programming time ............................................................................................... 106 table 7.7 flash memory oper ating states............................................................................ 111 section 10 timer a table 10.1 pin configuration.................................................................................................. 140 section 11 timer v table 11.1 pin configuration.................................................................................................. 147 table 11.2 clock signals to input to tc ntv and counting conditions ............................... 149 section 12 timer w table 12.1 timer w functions ............................................................................................... 160 table 12.2 pin configuration.................................................................................................. 162 section 14 s e rial comm u nicat i on i nte r f a ce 3 ( s ci 3 ) table 14.1 pin configuration.................................................................................................. 198 table 14.2 examples of brr settings for various b it rates (asynchronous mode) (1) ...... 206 table 14.2 examples of brr settings for various b it rates (asynchronous mode) (2) ...... 207 table 14.2 examples of brr settings for various b it rates (asynchronous mode) (3) ...... 208 table 14.3 maximum bit rate for each fre quency (asynchronous mode) .......................... 208 table 14.4 brr settings for various bit rates (c locked synchron ous mode)..................... 209 table 14.5 ssr status flags and recei ve data ha ndling ...................................................... 215 table 14.6 sci3 interrupt requests........................................................................................ 230 section 15 i 2 c bus interface (iic) table 15.1 i 2 c bus interface pins........................................................................................... 235 table 15.2 communication format ........................................................................................ 239 table 15.3 i 2 c transfer rate .................................................................................................. 241 table 15.4 flags and transf er states...................................................................................... 249 table 15.5 i 2 c bus timing (scl and sda output) .............................................................. 266 table 15.6 permissible scl rise time (t sr ) values ............................................................... 267 table 15.7 i 2 c bus timing (with maximum influence of t sr /t sf ) ............................................ 268 section 16 a/d converter table 16.1 pin configuration.................................................................................................. 277 table 16.2 analog input channels and corr esponding addr registers .............................. 278 table 16.3 a/d conversion time (single mode)................................................................... 283 section 17 eeprom table 17.1 pin configuration.................................................................................................. 289 table 17.2 slave addresses .................................................................................................... 292
rev. 6.00 mar. 24, 2006 page xxvii of xxviii section 20 electrical characteristics table 20.1 absolute maximum ratings ................................................................................. 311 table 20.2 dc characteris tics (1)........................................................................................... 314 table 20.2 dc characteris tics (2)........................................................................................... 318 table 20.2 dc characteris tics (3)........................................................................................... 319 table 20.3 ac character istics ................................................................................................ 320 table 20.4 i 2 c bus interface timing ...................................................................................... 322 table 20.5 serial interface (s ci3) timing ............................................................................. 323 table 20.6 a/d converter char acteristic s .............................................................................. 324 table 20.7 watchdog timer ch aracteristic s........................................................................... 325 table 20.8 flash memory char acteristic s .............................................................................. 326 table 20.9 eeprom character istics...................................................................................... 328 table 20.10 dc characteris tics (1)....................................................................................... 331 table 20.10 dc characteris tics (2)....................................................................................... 336 table 20.11 ac character istics ............................................................................................ 337 table 20.12 i 2 c bus interface timing .................................................................................. 339 table 20.13 serial interface (s ci3) timing ......................................................................... 340 table 20.14 a/d converter char acteristic s .......................................................................... 341 table 20.15 watchdog timer ch aracteristic s....................................................................... 342 appendix a instruction set table a.1 instruction set ....................................................................................................... 349 table a.2 operation code map (1) ....................................................................................... 362 table a.2 operation code map (2) ....................................................................................... 363 table a.2 operation code map (3) ....................................................................................... 364 table a.3 number of cycles in each instruction.................................................................. 366 table a.4 number of cycles in each instruction.................................................................. 367 table a.5 combinations of instructions and addressing modes .......................................... 376
rev. 6.00 mar. 24, 2006 page xxviii of xxviii
section 1 overview rev. 6.00 mar. 24, 2006 page 1 of 412 rej09b0142-0600 section 1 overview 1.1 features ? ? ? ? ? ? ? ? ? ? ? ? ? flash memory version h8/3664n HD64N3664 512 bytes 32 kbytes 2,048 bytes (f-ztat tm version) h8/3664f hd64f3664 ? 32 kbytes 2,048 bytes mask rom version h8/3664 hd6433664 ? 32 kbytes 1,024 bytes h8/3663 hd6433663 ? 24 kbytes 1,024 bytes h8/3662 hd6433662 ? 16 kbytes 512 bytes h8/3661 hd6433661 ? 12 kbytes 512 bytes h8/3660 hd6433660 ? 8 kbytes 512 bytes ? ? ? ? ?
section 1 overview rev. 6.00 mar. 24, 2006 page 2 of 412 rej09b0142-0600 ? ? lqfp-64 fp-64e 10.0 10.0 mm 0.5 mm qfp-64 fp-64a 14.0 14.0 mm 0.8 mm lqfp-48 fp-48f 10.0 10.0 mm 0.65 mm lqfp-48 fp-48b 7.0 7.0 mm 0.5 mm sdip-42 dp-42s 14.0 37.3 mm 1.78 mm only lqfp-64 (fp-64e) for h8/3664n package
section 1 overview rev. 6.00 mar. 24, 2006 page 3 of 412 rej09b0142-0600 1.2 internal block diagram p10/tmow p11 p12 p14/ irq0 p15/ irq1 p16/ irq2 p17/ irq3 /trgv p50/ wkp0 p51/ wkp1 p52/ wkp2 p53/ wkp3 p54/ wkp4 p55/ wkp5 / adtr g p56/sda p57/scl pb0/an0 pb1/an1 pb2/an2 pb3/an3 pb4/an4 pb5/an5 pb6/an6 pb7/an7 v cc v ss v cl res test nmi av cc p20/sck3 p21/rxd p22/txd p80/ftci p81/ftioa p82/ftiob p83/ftioc p84/ftiod p85 p86 p87 p74/tmriv p75/tmciv p76/tmov osc1 osc2 x1 x2 cpu h8/300h rom ram sci3 port 1 timer w i 2 c bus interface timer a watchdog timer timer v a/d converter subclock generator system clock generator port 2 port b port 5 port 7 port 8 data bus (upper) address bus data bus (lower) figure 1.1 internal block diagram of h8/3664 of f-ztat tm and mask-rom versions
section 1 overview rev. 6.00 mar. 24, 2006 page 4 of 412 rej09b0142-0600 p10/tmow p11 p12 p14/ irq0 p15/ irq1 p16/ irq2 p17/ irq3 /trgv p50/ wkp0 p51/ wkp1 p52/ wkp2 p53/ wkp3 p54/ wkp4 p55/ wkp5 / adtr g pb0/an0 pb1/an1 pb2/an2 pb3/an3 pb4/an4 pb5/an5 pb6/an6 pb7/an7 v cc v ss v cl res test nmi av cc p20/sck3 p21/rxd p22/txd sda scl p80/ftci p81/ftioa p82/ftiob p83/ftioc p84/ftiod p85 p86 p87 p74/tmriv p75/tmciv p76/tmov osc1 osc2 x1 x2 cpu h8/300h rom ram eeprom sci3 timer w i 2 c bus interface i 2 c bus timer a watchdog timer timer v a/d converter port 1 subclock generator system clock generator port 2 port 5 port b port 7 port 8 data bus (upper) address bus note : the h8/3664n is a stacked-structure product in which an eeprom chip is mounted on the h8/3664f-ztat tm version. data bus (lower) figure 1.2 internal block diagram of h8/3664n of f-ztat tm version with eeprom
section 1 overview rev. 6.00 mar. 24, 2006 page 5 of 412 rej09b0142-0600 1.3 pin arrangement nc nc av cc x2 x1 v cl res test v ss osc2 osc1 v cc p50/ wkp0 p51/ wkp1 nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 nc nc p22/txd p21/rxd p20/sck3 p87 p86 p85 p84/ftiod p83/ftioc p82/ftiob p81/ftioa p80/ftci nmi nc nc 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 nc nc p14/ irq0 p15/ irq1 p16/ irq2 p17/ irq3 /trgv pb4/an4 pb5/an5 pb6/an6 pb7/an7 pb3/an3 pb2/an2 pb1/an1 pb0/an0 nc nc nc nc p76/tmov p75/tmciv p74/tmriv p57/scl p56/sda p12 p11 p10/tmow p55/ wkp5 / adtr g p54/ wkp4 p53/ wkp3 p52/ wkp2 nc nc h8/3664 top view note: do not connect nc pins ( * these pins are not connected to the internal circuitry). figure 1.3 pin arrangement of h8/3664 of f-ztat tm and mask-rom versions (fp-64e, fp-64a)
section 1 overview rev. 6.00 mar. 24, 2006 page 6 of 412 rej09b0142-0600 avcc x2 x1 v cl res test v ss osc2 osc1 vcc p50/ wkp0 p51/ wkp1 123456789101112 37 38 39 40 41 42 43 44 45 46 47 48 36 35 34 33 32 31 30 29 28 27 26 25 p22/txd p21/rxd p20/sck3 p87 p86 p85 p84/ftiod p83/ftioc p82/ftiob p81/ftioa p80/ftci nmi 24 23 22 21 20 19 18 17 16 15 14 13 p14/ irq0 p15/ irq1 p16/ irq2 p17/ irq3 /trgv pb4/an4 pb5/an5 pb6/an6 pb7/an7 pb3/an3 pb2/an2 pb1/an1 pb0/an0 p76/tmov p75/tmciv p74/tmriv p57/scl p56/sda p12 p11 p10/tmow p55/ wkp5 / adtr g p54/ wkp4 p53/ wkp3 p52/ wkp2 h8/3664 top view figure 1.4 pin arrangement of h8/3664 of f-ztat tm and mask-rom versions (fp-48f, fp-48b)
section 1 overview rev. 6.00 mar. 24, 2006 page 7 of 412 rej09b0142-0600 pb3/an3 pb2/an2 pb1/an1 pb0/an0 av cc x2 x1 v cl res test v ss osc2 osc1 v cc p50/ wkp0 p51/ wkp1 p52/ wkp2 p53/ wkp3 p54/ wkp4 p55/ wkp5 / adtrg p10/tmow 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 p17/ irq3 /trgv p16/ irq2 p15/ irq1 p14/ irq0 p22/txd p21/rxd p20/sck3 p87 p86 p85 p84/ftiod p83/ftioc p82/ftiob p81/ftioa p80/ftci nmi p76/tmov p75/tmciv p74/tmriv p57/scl p56/sda 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 h8/3664 top view note: dp-42s has no p11, p12, pb4/an4, pb5/an5, pb6/an6, and pb7/an7 pins. figure 1.5 pin arrangement of h8/3664 of f-ztat tm and mask-rom versions (ds-42s)
section 1 overview rev. 6.00 mar. 24, 2006 page 8 of 412 rej09b0142-0600 nc nc avcc x2 x1 v cl res test v ss osc2 osc1 vcc p50/ wkp0 p51/ wkp1 nc nc 1 2 3 4 5 6 7 8 9 10111213141516 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 nc nc p22/txd p21/rxd p20/sck3 p87 p86 p85 p84/ftiod p83/ftioc p82/ftiob p81/ftioa p80/ftci nmi nc nc 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 nc nc p14/ irq0 p15/ irq1 p16/ irq2 p17/ irq3 /trgv pb4/an4 pb5/an5 pb6/an6 pb7/an7 pb3/an3 pb2/an2 pb1/an1 pb0/an0 nc nc nc nc p76/tmov p75/tmciv p74/tmriv scl * sda * p12 p11 p10/tmow p55/ wkp5 / adtr g p54/ wkp4 p53/ wkp3 p52/ wkp2 nc nc h8/3664n top view note: do not connect nc pins. * these pins are only available for the i 2 c bus interface in the f-zat tm version with eeprom. figure 1.6 pin arrangement of h8/3664n of f-ztat tm version with eeprom (fp-64e)
section 1 overview rev. 6.00 mar. 24, 2006 page 9 of 412 rej09b0142-0600 1.4 pin functions table 1.1 pin functions pin no. h8/3664 h8/3664n type symbol fp-64e, fp-64a fp-48f, fp-48b dp-42s fp-64e i/o functions power source pins v cc 12 10 14 12 input power supply pi n. connect this pin to the system power supply. v ss 9 7 11 9 input ground pin. connect all these pins to the system power supply (0v). av cc 3 1 5 3 input analog power supply pin for the a/d converter. when the a/d converter is not used, connect this pin to the system power supply. v cl 6 4 8 6 input internal step-down power supply pin. connect a capacitor of around 0.1 f between this pin and the vss pin for stabilization. clock pins osc1 11 9 13 11 input osc2 10 8 12 10 output these pins connect to a crystal or ceramic resonator for system clocks, or can be used to input an external clock. these pins can be used to input an external clock. see section 5, clock pulse generators, for a typical connection. x1 5 3 7 5 input for connection to a 32.768 khz crystal resonator for subclocks. see section 5, clock pulse generators, for a typical connection. x2 4 2 6 4 output system control res 7 5 9 7 input reset pin. when this driven low, the chip is reset. test 8 6 10 8 input test pin. connect this pin to vss.
section 1 overview rev. 6.00 mar. 24, 2006 page 10 of 412 rej09b0142-0600 pin no. h8/3664 h8/3664n type symbol fp-64e, fp-64a fp-48f, fp-48b dp-42s fp-64e i/o functions interrupt pins nmi 35 25 27 35 input non-maskable interrupt request input pin. be sure to pull-up by a pull-up resistor. irq0 to irq3 51 to 54 37 to 40 39 to 42 51 to 54 input external interrupt request input pins. can select the rising or falling edge. wkp0 to wkp5 13, 14, 19 to 22 11 to 16 15 to 20 13, 14, 19 to 22 input external interrupt request input pins. can select the rising or falling edge. timer a tmow 23 17 21 23 output this is an output pin for divided clocks timer v tmov 30 24 26 30 output this is an output pin for waveforms generated by the output compare function tmciv 29 23 25 29 input external event input pin tmriv 28 22 24 28 input counter reset input pin trgv 54 40 42 54 input counter start trigger input pin timer w ftci 36 26 28 36 input external event input pin ftioa to ftiod 37 to 40 27 to 30 29 to 32 37 to 40 i/o output compare output/ input capture input/ pwm output pin i 2 c bus inerface sda 26 * 2 20 22 26 * 1 i/o iic data i/o pin. c an directly drive a bus by nmos open-drain output. when using this pin, external pull-up resistance is required. scl 27 * 2 21 23 27 * 1 i/o (eeprom: input) iic clock i/o pin. can directly drive a bus by nmos open-drain output. when using this pin, external pull-up resistance is required. serial commu- nication txd 46 36 38 46 output transmit data output pin interface (sci) rxd 45 35 37 45 input receive data input pin sck3 44 34 36 44 i/o clock i/o pin a/d converter an7 to an0 55 to 62 41 to 48 1 to 4 * 2 55 to 62 input analog input pin adtrg 22 16 20 22 input a/d converter trigger input pin
section 1 overview rev. 6.00 mar. 24, 2006 page 11 of 412 rej09b0142-0600 pin no. h8/3664 h8/3664n type symbol fp-64e, fp-64a fp-48f, fp-48b dp-42s fp-64e i/o functions i/o ports pb7 to pb0 55 to 62 41 to 48 1 to 4 * 2 55 to 62 input 8-bit input port p17 to p14, p12 to p10 51 to 54 23 to 25 37 to 40 17 to 19 39 to 42, 21 * 2 51 to 54, 23 to 25 i/o 7-bit i/o port p22 to p20 44 to 46 34 to 36 36 to 38 44 to 46 i/o 3-bit i/o port p57 to p50 (p55 to p50 for h8/3664n) 13,14, 19 to 22 26, 27 21, 20, 16 to 11 15 to 20, 22, 23 13, 14, 19 to 22 i/o 8-bit i/o port (6-bit i/o port for h8/3664n) p76 to p74 28 to 30 22 to 24 24 to 26 28 to 30 i/o 3-bit i/o port p87 to p80 36 to 43 26 to 33 28 to 35 36 to 43 i/o 8-bit i/o port notes: 1. these pins are only available for the i 2 c bus interface in the f-zat tm version with eeprom. since the i 2 c bus is disabled after canceling a reset, the ic e bit in iccr must be set to 1 by using the program. 2. the dp-42s does not have the p11, p12, pb4/an4, pb5/an5, pb6/an6, and pb7/an7 pins.
section 1 overview rev. 6.00 mar. 24, 2006 page 12 of 412 rej09b0142-0600
section 2 cpu rev. 6.00 mar. 24, 2006 page 13 of 412 rej09b0142-0600 section 2 cpu this lsi has an h8/300h cpu with an internal 32-bit architecture that is upward-compatible with the h8/300cpu, and supports only normal mode, which has a 64-kbyte address space. ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
section 2 cpu rev. 6.00 mar. 24, 2006 page 14 of 412 rej09b0142-0600 2.1 address space and memory map the address space of this lsi is 64 kbytes, which includes th e program area and the data area. figures 2.1 show the memory map. interrupt vector on-chip rom (32 kbytes) not used (1-kbyte work area for flash memory programming) internal i/o register h'0000 h'0033 h'0034 h'7fff h'f780 h'fb7f h'ff7f h'ff80 h'fb80 h'ffff hd64f3664 (flash memory version) hd6433660 (mask rom version) hd6433661 (mask rom version) interrupt vector on-chip rom (8 kbytes) not used on-chip ram (512 bytes) internal i/o register h'0000 h'0033 h'0034 h'fd80 h'ff7f h'ff80 h'ffff h'1fff interrupt vector on-chip rom (12 kbytes) not used on-chip ram (512 bytes) internal i/o register h'0000 h'0033 h'0034 h'fd80 h'ff7f h'ff80 h'ffff h'2fff (1-kbyte user area) on-chip ram (2 kbytes) figure 2.1 memory map (1)
section 2 cpu rev. 6.00 mar. 24, 2006 page 15 of 412 rej09b0142-0600 interrupt vector on-chip rom (16 kbytes) on-chip ram (512 bytes) internal i/o register h'0000 h'0033 h'0034 h'3fff h'ff7f h'ff80 h'ffff hd6433664 (mask rom version) hd6433663 (mask rom version) hd6433662 (mask rom version) h'fd80 interrupt vector on-chip rom (24 kbytes) not used not used on-chip ram (1 kbyte) internal i/o register h'0000 h'0033 h'0034 h'5fff h'fb80 h'ff7f h'ff80 h'ffff interrupt vector on-chip rom (32 kbytes) not used on-chip ram (1 kbyte) internal i/o register h'0000 h'0033 h'0034 h'7fff h'fb80 h'ff7f h'ff80 h'ffff figure 2.1 memory map (2)
section 2 cpu rev. 6.00 mar. 24, 2006 page 16 of 412 rej09b0142-0600 HD64N3664 (on-chip eeprom module) user area (512 bytes) not used slave address register not used h'0000 h'01ff h'ff09 figure 2.1 memory map (3)
section 2 cpu rev. 6.00 mar. 24, 2006 page 17 of 412 rej09b0142-0600 2.2 register configuration the h8/300h cpu has the internal registers shown in figure 2.2. there are two types of registers; general registers and control registers. the control registers are a 24-bit program counter (pc), and an 8-bit condition code register (ccr). pc 23 0 15 0 7 0 7 0 e0 e1 e2 e3 e4 e5 e6 e7 r0h r1h r2h r3h r4h r5h r6h r7h r0l r1l r2l r3l r4l r5l r6l r7l sp: pc: ccr: i: ui: stack pointer program counter condition-code register interrupt mask bit user bit half-carry flag user bit negative flag zero flag overflow flag carry flag er0 er1 er2 er3 er4 er5 er6 er7 (sp) iuihunzvc ccr 76543210 h: u: n: z: v: c: general registers control registers (cr) [legend] figure 2.2 cpu registers
section 2 cpu rev. 6.00 mar. 24, 2006 page 18 of 412 rej09b0142-0600 2.2.1 general registers the h8/300h cpu has eight 32-bit general registers. these general registers are all functionally identical and can be used as both address register s and data registers. when a general register is used as a data register, it can be accessed as a 32-b it, 16-bit, or 8-bit regist er. figure 2.3 illustrates the usage of the general registers. when the genera l registers are used as 32-bit registers or address registers, they are designated by the letters er (er0 to er7). the er registers divide into 16-bit general registers designated by the letters e (e0 to e7) and r (r0 to r7). these registers are functionally equivalent, providing a maximum of sixteen 16-bit registers. the e registers (e0 to e7) are also referred to as extended registers. the r registers divide into 8-bit registers designated by the letters rh (r0h to r7h) and rl (r0l to r7l). these registers are functionally equivalent, providing a maximum of sixteen 8-bit registers. the usage of each register can be selected independently. general register er7 has the function of stack pointer (sp) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. figure 2.4 shows the stack. address registers 32-bit registers 16-bit registers 8-bit registers er registers (er0 to er7) e registers (extended registers) (e0 to e7) r registers (r0 to r7) rh registers (r0h to r7h) rl registers (r0l to r7l) figure 2.3 usage of general registers
section 2 cpu rev. 6.00 mar. 24, 2006 page 19 of 412 rej09b0142-0600 sp (er7) free area stack area figure 2.4 relationship between stack pointer and stack area 2.2.2 program counter (pc) this 24-bit counter indicates the address of the ne xt instruction the cpu will execute. the length of all cpu instructions is 2 bytes (one word), so the least significant pc bit is ignored. (when an instruction is fetched, the least significant pc bit is regarded as 0). the pc is initialized when the start address is loaded by the vector address generated during reset exception-handling sequence. 2.2.3 condition-code register (ccr) this 8-bit register contains internal cpu status information, including an interrupt mask bit (i) and half-carry (h), negative (n), zero (z), overflow (v ), and carry (c) flags. the i bit is initialized to 1 by reset exception-handling sequence, but other bits are not initialized. some instructions leave flag bits unchanged. op erations can be performed on the ccr bits by the ldc, stc, andc, orc, and xorc instructions. the n, z, v, and c flags are used as branching conditions for conditional branch (bcc) instructions. for the action of each instru c tion on the flag bits, see app e ndix a . 1, instruction list.
section 2 cpu rev. 6.00 mar. 24, 2006 page 20 of 412 rej09b0142-0600 bit bit name initial value r/w description 7 i 1 r/w interrupt mask bit masks interrupts other than nmi when set to 1. nmi is accepted regardless of the i bit setting. the i bit is set to 1 at the start of an e xception-handling sequence. 6 ui undefined r/w user bit can be written and read by software using the ldc, stc, andc, orc, and xorc instructions. 5 h undefined r/w half-carry flag when the add.b, addx.b, sub.b, subx.b, cmp.b, or neg.b instruction is execut ed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. when the add.w, sub.w, cmp.w, or neg.w instruction is executed, the h flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. when the add.l, sub.l, cmp.l, or neg.l instruction is executed, the h fl ag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. 4 u undefined r/w user bit can be written and read by software using the ldc, stc, andc, orc, and xorc instructions. 3 n undefined r/w negative flag stores the value of the most significant bit of data as a sign bit. 2 z undefined r/w zero flag set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. 1 v undefined r/w overflow flag set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. 0 c undefined r/w carry flag set to 1 when a carry occurs, and cleared to 0 otherwise. used by: add instructions, to indicate a carry subtract instructions, to indicate a borrow shift and rotate instructi ons, to indicate a carry the carry flag is also used as a bit accumulator by bit manipulation instructions.
section 2 cpu rev. 6.00 mar. 24, 2006 page 21 of 412 rej09b0142-0600 2.3 data formats the h8/300h cpu can process 1-bit, 4-bit (bcd), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ?, 7) of byte operand data. the daa and das decimal-adjust instructions treat byte data as two digits of 4-bit bcd data. 2.3.1 general register data formats figure 2.5 shows the data formats in general registers. 7 0 7 0 msb lsb msb lsb 70 4 3 don't care don't care don't care 7 0 4 3 70 don't care 65432 71 0 7 0 don't care 65432 710 don't care rnh rnl rnh rnl rnh rnl data type general register data format byte data byte data 4-bit bcd data 4-bit bcd data 1-bit data 1-bit data upper lower upper lower figure 2.5 general register data formats (1)
section 2 cpu rev. 6.00 mar. 24, 2006 page 22 of 412 rej09b0142-0600 15 0 msb lsb 15 0 msb lsb 31 16 msb 15 0 lsb ern: en: rn: rnh: rnl: msb: lsb: general register er general register e general register r general register rh general register rl most significant bit least significant bit data type data format general register word data word data rn en longword data [legend] ern figure 2.5 general register data formats (2)
section 2 cpu rev. 6.00 mar. 24, 2006 page 23 of 412 rej09b0142-0600 2.3.2 memory data formats figure 2.6 shows the data formats in memory. the h8/300h cpu can access word data and longword data in memory, however word or longword data must begin at an even address. if an attempt is made to access word or longword data at an odd addr ess, an address error does not occur, however the least significant bit of the address is re garded as 0, so access begins the preceding address. this also applies to instruction fetches. when er7 (sp) is used as an address register to access the stack, the operand size should be word or longword. 70 76 543210 msb lsb msb msb lsb lsb data type address 1-bit data byte data word data address l address l address 2m address 2m+1 longword data address 2n address 2n+1 address 2n+2 address 2n+3 data format figure 2.6 memory data formats
section 2 cpu rev. 6.00 mar. 24, 2006 page 24 of 412 rej09b0142-0600 2.4 instruction set 2.4.1 table of instructions classified by function the h8/300h cpu has 62 instructions. tables 2.2 to 2.9 summarize the instructions in each functional category. the notation used in tables 2.2 to 2.9 is defined below. table 2.1 operation notation symbol description rd general register (destination) * rs general register (source) * rn general register * ern general register (32-bit register or address register) (ead) destination operand (eas) source operand ccr condition-code register n n (negative) flag in ccr z z (zero) flag in ccr v v (overflow) flag in ccr c c (carry) flag in ccr pc program counter sp stack pointer #imm immediate data disp displacement + addition ? subtraction multiplication division logical and logical or logical xor move ? not (logical complement) :3/:8/:16/:24 3-, 8-, 16-, or 24-bit length note: * general registers include 8-bit registers (r 0h to r7h, r0l to r7l), 16-bit registers (r0 to r7, e0 to e7), and 32-bit regi sters/address register (er0 to er7).
section 2 cpu rev. 6.00 mar. 24, 2006 page 25 of 412 rej09b0142-0600 table 2.2 data transfer instructions instruction size * function mov b/w/l (eas) rd, rs (ead) moves data between two general registers or between a general register and memory, or moves immediate data to a general register. movfpe b (eas) rd, cannot be used in this lsi. movtpe b rs (eas) cannot be used in this lsi. pop w/l @sp+ rn pops a general register from the stack. pop.w rn is identical to mov.w @sp+, rn. pop.l ern is id entical to mov.l @sp+, ern. push w/l rn @?sp pushes a general register onto the stack. push.w rn is identical to mov.w rn, @?sp. push.l ern is identical to mov.l ern, @?sp. note: * refers to the operand size. b: byte w: word l: longword
section 2 cpu rev. 6.00 mar. 24, 2006 page 26 of 412 rej09b0142-0600 table 2.3 arithmetic operations instructions (1) instruction size * function add sub b/w/l rd rs rd, rd #imm rd performs addition or subtraction on da ta in two general registers, or on immediate data and data in a general register (immediate byte data cannot be subtracted from byte dat a in a general register. use the subx or add instruction.) addx subx b rd rs c rd, rd #imm c rd performs addition or subtraction with carry on byte data in two general registers, or on immediate data and data in a general register. inc dec b/w/l rd 1 rd, rd 2 rd increments or decrements a general re gister by 1 or 2. (byte operands can be incremented or decremented by 1 only.) adds subs l rd 1 rd, rd 2 rd, rd 4 rd adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. daa das b rd decimal adjust rd decimal-adjusts an addition or subtracti on result in a general register by referring to the ccr to produce 4-bit bcd data. mulxu b/w rd rs rd performs unsigned multiplication on data in two general registers: either 8 bits 8 bits 16 bits or 16 bits 16 bits 32 bits. mulxs b/w rd rs rd performs signed multiplication on data in two general registers: either 8 bits 8 bits 16 bits or 16 bits 16 bits 32 bits. divxu b/w rd rs rd performs unsigned division on data in two general registers: either 16 bits 8 bits 8-bit quotient and 8-bit remainder or 32 bits 16 bits 16-bit quotient and 16-bit remainder. note: * refers to the operand size. b: byte w: word l: longword
section 2 cpu rev. 6.00 mar. 24, 2006 page 27 of 412 rej09b0142-0600 table 2.3 arithmetic operations instructions (2) instruction size * function divxs b/w rd rs rd performs signed division on data in two general registers: either 16 bits 8 bits 8-bit quotient and 8-bit remainder or 32 bits 16 bits 16-bit quotient and 16-bit remainder. cmp b/w/l rd ? rs, rd ? #imm compares data in a general regist er with data in another general register or with immediate data, and sets ccr bits according to the result. neg b/w/l 0 ? rd rd takes the two's complement (arith metic complement) of data in a general register. extu w/l rd (zero extension) rd extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. exts w/l rd (sign extension) rd extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit. note: * refers to the operand size. b: byte w: word l: longword
section 2 cpu rev. 6.00 mar. 24, 2006 page 28 of 412 rej09b0142-0600 table 2.4 logic operations instructions instruction size * function and b/w/l rd rs rd, rd #imm rd performs a logical and operation on a general register and another general register or immediate data. or b/w/l rd rs rd, rd #imm rd performs a logical or operation on a general register and another general register or immediate data. xor b/w/l rd rs rd, rd #imm rd performs a logical exclusive or operation on a general register and another general register or immediate data. not b/w/l ? (rd) (rd) takes the one's complement of general register contents. note: * refers to the operand size. b: byte w: word l: longword table 2.5 shift instructions instruction size * function shal shar b/w/l rd (shift) rd performs an arithmetic shift on general register contents. shll shlr b/w/l rd (shift) rd performs a logical shift on general register contents. rotl rotr b/w/l rd (rotate) rd rotates general register contents. rotxl rotxr b/w/l rd (rotate) rd rotates general register contents through the carry flag. note: * refers to the operand size. b: byte w: word l: longword
section 2 cpu rev. 6.00 mar. 24, 2006 page 29 of 412 rej09b0142-0600 table 2.6 bit manipulation instructions (1) instruction size * function bset b 1 ( of ) sets a specified bit in a general register or memory operand to 1. the bit number is specified by 3-bit immediat e data or the lower three bits of a general register. bclr b 0 ( of ) clears a specified bit in a general register or memory operand to 0. the bit number is specified by 3-bit immedi ate data or the lower three bits of a general register. bnot b ? ( of ) ( of ) inverts a specified bit in a general register or memory operand. the bit number is specified by 3-bit immediat e data or the lower three bits of a general register. btst b ? ( of ) z tests a specified bit in a general register or memory operand and sets or clears the z flag accordingly. t he bit number is specified by 3-bit immediate data or the lower three bits of a general register. band biand b b c ( of ) c ands the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. c ? ( of ) c ands the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. the bit number is specified by 3-bit immediate data. bor bior b b c ( of ) c ors the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. c ? ( of ) c ors the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. the bit number is specified by 3-bit immediate data. note: * refers to the operand size. b: byte
section 2 cpu rev. 6.00 mar. 24, 2006 page 30 of 412 rej09b0142-0600 table 2.6 bit manipulation instructions (2) instruction size * function bxor bixor b b c ( of ) c xors the carry flag with a specified bi t in a general register or memory operand and stores the result in the carry flag. c ? ( of ) c xors the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. the bit number is specified by 3-bit immediate data. bld bild b b ( of ) c transfers a specified bit in a general register or memory operand to the carry flag. ? ( of ) c transfers the inverse of a specified bit in a general register or memory operand to the carry flag. the bit number is specified by 3-bit immediate data. bst bist b b c ( of ) transfers the carry flag value to a specified bit in a general register or memory operand. ? c ( of ) transfers the inverse of the carry flag value to a specified bit in a general register or memory operand. the bit number is specified by 3-bit immediate data. note: * refers to the operand size. b: byte
section 2 cpu rev. 6.00 mar. 24, 2006 page 31 of 412 rej09b0142-0600 table 2.7 branch instructions instruction size function bcc * ? branches to a specified address if a specified condition is true. the branching conditions are listed below. mnemonic description condition bra (bt) always (true) always brn (bf) never (false) never bhi high c z = 0 bls low or same c z = 1 bcc (bhs) carry clear (high or same) c = 0 bcs (blo) carry set (low) c = 1 bne not equal z = 0 beq equal z = 1 bvc overflow clear v = 0 bvs overflow set v = 1 bpl plus n = 0 bmi minus n = 1 bge greater or equal n v = 0 blt less than n v = 1 bgt greater than z (n v) = 0 ble less or equal z (n v) = 1 jmp ? branches unconditionally to a specified address. bsr ? branches to a subroutine at a specified address. jsr ? branches to a subroutine at a specified address. rts ? returns from a subroutine note: * bcc is the general name for conditional branch instructions.
section 2 cpu rev. 6.00 mar. 24, 2006 page 32 of 412 rej09b0142-0600 table 2.8 system control instructions instruction size * function trapa ? starts trap-instruct ion excepti on handling. rte ? returns from an exception-handling routine. sleep ? causes a transition to a power-down state. ldc b/w (eas) ccr moves the source operand contents to the ccr. the ccr size is one byte, but in transfer from memory, data is read by word access. stc b/w ccr (ead), exr (ead) transfers the ccr contents to a destination location. the condition code register size is one byte, but in transfer to memory, data is written by word access. andc b ccr #imm ccr, exr #imm exr logically ands the ccr with immediate data. orc b ccr #imm ccr, exr #imm exr logically ors the ccr with immediate data. xorc b ccr #imm ccr, exr #imm exr logically xors the ccr with immediate data. nop ? pc + 2 pc only increments the program counter. note: * refers to the operand size. b: byte w: word
section 2 cpu rev. 6.00 mar. 24, 2006 page 33 of 412 rej09b0142-0600 table 2.9 block data transfer instructions instruction size function eepmov.b ? if r4l 0 then repeat @er5+ @er6+, r4l?1 r4l until r4l = 0 else next; eepmov.w ? if r4 0 then repeat @er5+ @er6+, r4?1 r4 until r4 = 0 else next; transfers a data block. starting from the address set in er5, transfers data for the number of bytes set in r4l or r4 to the address location set in er6. execution of the next instruction be gins as soon as the transfer is completed.
section 2 cpu rev. 6.00 mar. 24, 2006 page 34 of 412 rej09b0142-0600 2.4.2 basic instruction formats h8/300h cpu instructions consist of 2-byte (1-word) units. an instruction consists of an operation field (op field), a register field (r field) , an effective address extension (ea field), and a condition field (cc). figure 2.7 shows examples of instruction formats. ? ? ? ? op op rn rm nop, rts, etc. add.b rn, rm, etc. mov.b @(d:16, rn), rm rn rm op ea(disp) op cc ea(disp) bra d:8 (1) operation field only (2) operation field and register fields (3) operation field, register fields, and effective address extension (4) operation field, effective address extension, and condition field figure 2.7 instruction formats
section 2 cpu rev. 6.00 mar. 24, 2006 page 35 of 412 rej09b0142-0600 2.5 addressing modes and effective address calculation the following describes the h8/300h cpu. in this lsi, the upper eight bits are ignored in the generated 24-bit address, so the effective address is 16 bits. 2.5.1 addressing modes the h8/300h cpu supports the eight addressing modes listed in table 2.10. each instruction uses a subset of these addressing modes. addressing modes that can be used differ depending on the instruction. for details, refer to appendix a.4, combinations of instructions and addressing modes. arithmetic and logic instructions can use the regist er direct and immediate modes. data transfer instructions can use all addressing modes except program-counter relative and memory indirect. bit manipulation instructions use register direct, register indirect, or the absolute addressing mode to specify an operand, and re gister direct (bset, bclr, bnot, and btst instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. table 2.10 addressing modes no. addressing mode symbol 1 register direct rn 2 register indirect @ern 3 register indirect with displa cement @(d:16,ern)/@(d:24,ern) 4 register indirect with post-increment register indirect with pre-decrement @ern+ @?ern 5 absolute address @aa:8/@aa:16/@aa:24 6 immediate #xx: 8/#xx:16/#xx:32 7 program-counter relati ve @(d:8,pc)/@(d:16,pc) 8 memory indirect @@aa:8
section 2 cpu rev. 6.00 mar. 24, 2006 page 36 of 412 rej09b0142-0600 (1) register direct?rn the register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. r0h to r7h and r0l to r7l can be specified as 8-bit registers. r0 to r7 and e0 to e7 can be specified as 16-bit registers. er0 to er7 can be specified as 32-bit registers. (2) register indirect?@ern the register field of the instruction code specifies an address register (ern), the lower 24 bits of which contain the address of the operand on memory. (3) register indirect with displacemen t?@(d:16, ern) or @(d:24, ern) a 16-bit or 24-bit displacement cont ained in the instruction is adde d to an address register (ern) specified by the register field of the instruction, and the lower 24 bits of the sum the address of a memory operand. a 16-bit displacemen t is sign-extended when added. (4) register indirect with post-incremen t or pre-decrement?@ern+ or @-ern (a) register indirect with post-increment?@ern+ the register field of the instruction code specifies an address register (ern) the lower 24 bits of which contains the address of a me mory operand. after the operand is accessed, 1, 2, or 4 is added to the address register contents (32 bits) and the sum is stored in the address register. the value added is 1 for byte access, 2 for word access, or 4 for longword access. for the word or longword access, the register value should be even. (b) register indirect with pre-decrement?@-ern the value 1, 2, or 4 is subtracted from an addres s register (ern) specified by the register field in the instruction code, and the lower 24 bits of the result is the address of a memory operand. the result is also stored in the address register. the value subtracted is 1 for byte access, 2 for word access, or 4 for longword access. fo r the word or longword access, the register value should be even.
section 2 cpu rev. 6.00 mar. 24, 2006 page 37 of 412 rej09b0142-0600 (5) absolute address?@aa:8, @aa:16, @aa:24 the instruction code contains the absolute addr ess of a memory operand. the absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24) for an 8-bit absolute address, the upper 16 bits are all assumed to be 1 (h'ffff). for a 16-bit absolute address the upper 8 bits are a sign ex tension. a 24-bit absolute address can access the entire address space. the access ranges of absolute addr esses for the group of this lsi are those shown in table 2.11, because the upper 8 bits are ignored. table 2.11 absolute address access ranges absolute address access range 8 bits (@aa:8) h'ff00 to h'ffff 16 bits (@aa:16) h'0000 to h'ffff 24 bits (@aa:24) h'0000 to h'ffff (6) immediate?#xx:8, #xx:16, or #xx:32 the instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. the adds, subs, inc, and dec instructions contain immediate data implicitly. some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. the trapa instruction contains 2-bit immediate data in its instruction code, specifying a vector address. (7) program-counter relative?@(d:8, pc) or @(d:16, pc) this mode is used in the bsr instruction. an 8-b it or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit pc contents to generate a branch address. the pc value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is ?126 to +128 bytes (?63 to +64 words) or ?32766 to +32768 bytes (?16383 to +16384 words) from the branch instruction. the resulting value should be an even number.
section 2 cpu rev. 6.00 mar. 24, 2006 page 38 of 412 rej09b0142-0600 (8) memory indirect?@@aa:8 this mode can be used by the jmp and jsr instructions. the instruction code contains an 8-bit absolute address specifying a memo ry operand. this memory operand contains a branch address. the memory operand is accessed by longword access. the first byt e of the memory operand is ignored, generating a 24-bit branch address. figure 2.8 shows how to specify branch address for in memory indirect mode. the upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (h'0000 to h'00ff). note that the first part of the address range is also the exception vector area. specified by @aa:8 branch address dummy figure 2.8 branch a ddress specification in memory indirect mode
section 2 cpu rev. 6.00 mar. 24, 2006 page 39 of 412 rej09b0142-0600 2.5.2 effective address calculation table 2.12 indicates how effectiv e addresses are calculated in each addressing mode. in this lsi the upper 8 bits of the ef fective address are ignored in order to generate a 16-bit effective address. table 2.12 effective ad dress calculation (1) no 1 r o p 31 0 23 2 3 registe r indirect with dis placement @(d: 16,ern) or @(d: 24,ern) 4 r o p disp r op rm op rn 3 1 0 0 r o p 2 3 0 31 0 dis p 31 0 31 0 23 0 23 0 addressing mode and instruction format effective address calculation effective address (ea) register direct(rn) general register contents general register contents general register contents general register contents sign extension register indirect(@ern) register indirect with post-increment or pre-decrement register indirect with post-increment @ern+ register indirect with pre-decrement @-ern 1, 2, or 4 1, 2, or 4 operand is general register contents. the value to be added or subtracted is 1 when the operand is byte size, 2 for word size, and 4 for longword size.
section 2 cpu rev. 6.00 mar. 24, 2006 page 40 of 412 rej09b0142-0600 table 2.12 effective ad dress calculation (2) no 5 op 23 0 abs @aa:8 7 h'ffff op 23 0 @aa:16 @aa:24 abs 15 16 23 0 o p abs 6 o p imm #xx:8/#xx:16/#xx:32 8 addressing mode and instruction format absolute address immediate effective address calculation effective address (ea) sign extension operand is immediate data. 7 p rogr am- counter re lativ e @ (d:8 ,pc ) @( d:16 ,pc) m em ory indirect @@aa :8 23 0 di s p 0 23 0 di s p op 23 op 8 abs 23 0 abs h' 0000 7 8 0 1 5 23 0 1 5 h' 00 16 [legend] r, rm,rn : op : disp : imm : abs : register field operation field displacement immediate data absolute address pc contents sign extension memory contents
section 2 cpu rev. 6.00 mar. 24, 2006 page 41 of 412 rej09b0142-0600 2.6 basic bus cycle cpu operation is synchronized by a system clock ( t 1 state bus cycle t 2 state internal address bus or sub internal read signal internal data bus (read access) internal write signal read data address write data internal data bus (write access) figure 2.9 on-chip memory access cycle
section 2 cpu rev. 6.00 mar. 24, 2006 page 42 of 412 rej09b0142-0600 2.6.2 on-chip peripheral modules on-chip peripheral modules are accessed in two states or three states. the data bus width is 8 bits or 16 bits depending on the register. for description on the data bus width and number of accessing states of each register, refer to sect ion 19.1, register addresses (address order). registers with 16-bit data bus width can be accessed by word size only. registers with 8-bit data bus width can be accessed by byte or word size. wh en a register with 8-bit data bus width is accessed by word size, access is completed in two cy cles. in two-state access, the operation timing is the same as that for on-chip memory. figure 2.10 shows the operation timing in the case of three-state access to an on-chip peripheral module. t 1 state bus cycle internal address bus internal read signal internal data bus (read access) internal write signal read data address internal data bus (write access) t 2 state t 3 state write data or sub figure 2.10 on-chip peripheral mo dule access cycle (3-state access)
section 2 cpu rev. 6.00 mar. 24, 2006 page 43 of 412 rej09b0142-0600 2.7 cpu states there are four cpu states: the re set state, program execution st ate, program halt state, and exception-handling state. the program execution state includes active mode and subactive mode. in the program halt state there are a sleep mode, standby mode, and sub-sleep mode. these states are shown in figure 2.11. figure 2.12 shows the state transitions. for details on program execution state and program halt state, refer to section 6, power-down modes. for details on exception processing, refer to section 3, exception handling. cpu state reset state program execution state program halt state exception- handling state active (high speed) mode subactive mode sleep mode subsleep mode power-down modes the cpu executes successive program instructions at high speed, synchronized by the system clock the cpu executes successive program instructions at reduced speed, synchronized by the subclock a state in which some or all of the chip functions are stopped to conserve power a transient state in which the cpu changes the processing flow due to a reset or an interrupt the cpu is initialized standby mode figure 2.11 cpu operation states
section 2 cpu rev. 6.00 mar. 24, 2006 page 44 of 412 rej09b0142-0600 reset state program halt state exception-handling state program execution state reset cleared sleep instruction executed reset occurs interrupt source reset occurs interrupt source exception- handling complete reset occurs figure 2.12 state transitions 2.8 usage notes 2.8.1 notes on data access to empty areas the address space of this lsi includes empty areas in additio n to the rom, ram, and on-chip i/o registers areas available to the user. when da ta is transferred from cpu to empty areas, the transferred data will be lost. this action may al so cause the cpu to malfunction. when data is transferred from an empty ar ea to cpu, the contents of the data cannot be guaranteed. 2.8.2 eepmov instruction eepmov is a block-transfer instru ction and transfers th e byte size of data indicated by r4l, which starts from the address indicated by r5, to the address indicated by r6. set r4l and r6 so that the end address of the destination address (value of r6 +
section 2 cpu rev. 6.00 mar. 24, 2006 page 45 of 412 rej09b0142-0600 2.8.3 bit manipulation instruction the bset, bclr, bnot, bst, and bist instructions read data from the specified address in byte units, manipulate the data of the target bit, an d write data to the same address again in byte units. special care is required wh en using these instructions in cases where two registers are assigned to the same address or when a bit is directly manipulated for a port, because this may rewrite data of a bit other than the bit to be manipulated. (1) bit manipulation for two registers assigned to the same address example 1: bit manipulation for the timer load register and timer counter (applicable for timer b and timer c, not for the group of this lsi.) figure 2.13 shows an example of a timer in which two timer registers are assigned to the same address. when a bit manipulation instruction accesses the timer load register and timer counter of a reloadable timer, since these two registers share the same address, the following operations takes place. 1. data is read in byte units. 2. the cpu sets or resets the bit to be manipulated with the bit manipulation instruction. 3. the written data is written again in byte units to the timer load register. the timer is counting, so the value read is not necessarily the same as the value in the timer load register. as a result, bits other than the intended bit in the timer counter may be modified and the modified value may be written to the timer load register. read write count clock timer counter timer load register reload internal bus figure 2.13 example of timer configuration with two registers allocated to same address
section 2 cpu rev. 6.00 mar. 24, 2006 page 46 of 412 rej09b0142-0600 example 2: the bset instruction is executed for port 5. p57 and p56 are input pins, with a low-level signal input at p57 and a high-level signal input at p56. p55 to p50 are output pins and output low-level signals. an example to output a high-level signal at p50 with a bset instruction is shown below. prior to executing bset p57 p56 p55 p54 p53 p52 p51 p50 input/output input input output output output output output output pin state low level high level low level low level low level low level low level low level pcr5 0 0 1 1 1 1 1 1 pdr5 1 0 0 0 0 0 0 0 bset instruction executed bset #0, @pdr5 the bset instruction is executed for port 5. after executing bset p57 p56 p55 p54 p53 p52 p51 p50 input/output input input output output output output output output pin state low level high level low level low level low level low level low level high level pcr5 0 0 1 1 1 1 1 1 pdr5 0 1 0 0 0 0 0 1 description on operation when the bset instruction is execut ed, first the cpu reads port 5. since p57 and p56 are input pins, the cpu reads the pin states (low-level an d high-level input). p55 to p50 are output pins, so the cpu reads the value in pdr5. in this example pdr5 has a value of h'80, but the value read by the cpu is h'40. next, the cpu sets bit 0 of the read data to 1, changing the pdr5 data to h'41. finally, the cpu writes h'41 to pdr5, completing execution of bset.
section 2 cpu rev. 6.00 mar. 24, 2006 page 47 of 412 rej09b0142-0600 as a result of the bset instruction, bit 0 in pdr5 becomes 1, and p50 outputs a high-level signal. however, bits 7 and 6 of pdr5 end up with different values. to prevent this problem, store a copy of the pdr5 data in a work area in memory. perform the bit manipulation on the data in the work area, then write this data to pdr5. prior to executing bset mov.b #80, r0l mov.b r0l, @ram0 mov.b r0l, @pdr5 the pdr5 value (h'80) is written to a work area in memory (ram0) as well as to pdr5. p57 p56 p55 p54 p53 p52 p51 p50 input/output input input output output output output output output pin state low level high level low level low level low level low level low level low level pcr5 0 0 1 1 1 1 1 1 pdr5 1 0 0 0 0 0 0 0 ram0 1 0 0 0 0 0 0 0 bset instruction executed bset #0, @ram0 the bset instruction is executed designating the pdr5 work area (ram0). after executing bset mov.b @ram0, r0l mov.b r0l, @pdr5 the work area (ram0) value is written to pdr5. p57 p56 p55 p54 p53 p52 p51 p50 input/output input input output output output output output output pin state low level high level low level low level low level low level low level high level pcr5 0 0 1 1 1 1 1 1 pdr5 1 0 0 0 0 0 0 1 ram0 1 0 0 0 0 0 0 1
section 2 cpu rev. 6.00 mar. 24, 2006 page 48 of 412 rej09b0142-0600 (2) bit manipulation in a register containing a write-only bit example 3: bclr instruction executed designating port 5 control register pcr5 p57 and p56 are input pins, with a low-level signal input at p57 and a high-level signal input at p56. p55 to p50 are output pins that output low-level signals. an example of setting the p50 pin as an input pin by the bclr instruction is shown below. it is assumed that a high-level signal will be input to this input pin. prior to executing bclr p57 p56 p55 p54 p53 p52 p51 p50 input/output input input output output output output output output pin state low level high level low level low level low level low level low level low level pcr5 0 0 1 1 1 1 1 1 pdr5 1 0 0 0 0 0 0 0 bclr instruction executed bclr #0, @pcr5 the bclr instruction is executed for pcr5. after executing bclr p57 p56 p55 p54 p53 p52 p51 p50 input/output output output output output output ou tput output input pin state low level high level low level low level low level low level low level high level pcr5 1 1 1 1 1 1 1 0 pdr5 1 0 0 0 0 0 0 0 description on operation when the bclr instruction is ex ecuted, first the cpu reads pcr5 . since pcr5 is a write-only register, the cpu reads a valu e of h'ff, even though the pcr5 value is actually h'3f. next, the cpu clears bit 0 in the read data to 0, changing the data to h'fe. finally, h'fe is written to pcr5 and bclr instruction execution ends.
section 2 cpu rev. 6.00 mar. 24, 2006 page 49 of 412 rej09b0142-0600 as a result of this operation, bit 0 in pcr5 becomes 0, making p50 an input port. however, bits 7 and 6 in pcr5 change to 1, so that p57 and p56 change from input pins to output pins. to prevent this problem, store a copy of the pdr5 data in a work area in memory and manipulate data of the bit in the work area, then write this data to pdr5. prior to executing bclr mov.b #3f, r0l mov.b r0l, @ram0 mov.b r0l, @pcr5 the pcr5 value (h'3f) is written to a work area in memory (ram0) as well as to pcr5. p57 p56 p55 p54 p53 p52 p51 p50 input/output input input output output output output output output pin state low level high level low level low level low level low level low level low level pcr5 0 0 1 1 1 1 1 1 pdr5 1 0 0 0 0 0 0 0 ram0 0 0 1 1 1 1 1 1 bclr instruction executed bclr #0, @ram0 the bclr instructions executed for the pcr5 work area (ram0). after executing bclr mov.b @ram0, r0l mov.b r0l, @pcr5 the work area (ram0) value is written to pcr5. p57 p56 p55 p54 p53 p52 p51 p50 input/output input input output output output out put output output pin state low level high level low level low level low level low level low level high level pcr5 0 0 1 1 1 1 1 0 pdr5 1 0 0 0 0 0 0 0 ram0 0 0 1 1 1 1 1 0
section 2 cpu rev. 6.00 mar. 24, 2006 page 50 of 412 rej09b0142-0600
section 3 exception handling rev. 6.00 mar. 24, 2006 page 51 of 412 rej09b0142-0600 section 3 exception handling exception handling may be caused by a reset, a trap instruction (trapa), or interrupts. ? res pin. the chip is also reset when the watchdog timer overflows, and exception handling starts. exception handling is the same as exception handling by the res pin. ? ?
section 3 exception handling rev. 6.00 mar. 24, 2006 page 52 of 412 rej09b0142-0600 table 3.1 exception sou rces and vector address relative module exception sources vector number vector address priority res pin watchdog timer reset 0 h'0000 to h'0001 high ? reserved for system use 1 to 6 h'0002 to h'000d external interrupt pin nmi 7 h'000e to h'000f trap instruction (#0) 8 h'0010 to h'0011 (#1) 9 h'0012 to h'0013 (#2) 10 h'0014 to h'0015 cpu (#3) 11 h'0016 to h'0017 address break break conditions satisfied 12 h'0018 to h'0019 cpu direct transition by executing the sleep instruction 13 h'001a to h'001b irq0 14 h'001c to h'001d irq1 15 h'001e to h'001f irq2 16 h'0020 to h'0021 irq3 17 h'0022 to h'0023 external interrupt pin wkp 18 h'0024 to h'0025 timer a overflow 19 h'0026 to h'0027 ? reserved for system use 20 h'0028 to h'0029 timer w input capture a/compare match a input capture b/compare match b input capture c/compare match c input capture d/compare match d timer w overflow 21 h'002a to h'002b timer v timer v compare match a timer v compare match b timer v overflow 22 h'002c to h'002d sci3 sci3 receive data full sci3 transmit data empty sci3 transmit end sci3 receive error 23 h'002e to h'002f iic data transfer end address inequality stop conditions detected 24 h'0030 to h'0031 a/d converter a/d conversion end 25 h'0032 to h'0033 low
section 3 exception handling rev. 6.00 mar. 24, 2006 page 53 of 412 rej09b0142-0600 3.2 register descriptions interrupts are controlled by the following registers. ? ? ? ? ? nmi and irq3 to irq0 . bit bit name initial value r/w description 7 nmieg 0 r/w nmi edge select 0: falling edge of nmi pin input is detected 1: rising edge of nmi pin input is detected 6 5 4 ? ? ? 1 1 1 ? ? ? reserved these bits are always read as 1. 3 ieg3 0 r/w irq3 edge select 0: falling edge of irq3 pin input is detected 1: rising edge of irq3 pin input is detected 2 ieg2 0 r/w irq2 edge select 0: falling edge of irq2 pin input is detected 1: rising edge of irq2 pin input is detected 1 ieg1 0 r/w irq1 edge select 0: falling edge of irq1 pin input is detected 1: rising edge of irq1 pin input is detected 0 ieg0 0 r/w irq0 edge select 0: falling edge of irq0 pin input is detected 1: rising edge of irq0 pin input is detected
section 3 exception handling rev. 6.00 mar. 24, 2006 page 54 of 412 rej09b0142-0600 3.2.2 interrupt edge se lect register 2 (iegr2) iegr2 selects the direction of an edge that generates interrupt requests of the pins adtrg and wkp5 to wkp0 . bit bit name initial value r/w description 7 6 ? ? 1 1 ? ? reserved these bits are always read as 1. 5 wpeg5 0 r/w wkp5 edge select 0: falling edge of wkp5 ( adtrg ) pin input is detected 1: rising edge of wkp5 ( adtrg ) pin input is detected 4 wpeg4 0 r/w wkp4 edge select 0: falling edge of wkp4 pin input is detected 1: rising edge of wkp4 pin input is detected 3 wpeg3 0 r/w wkp3 edge select 0: falling edge of wkp3 pin input is detected 1: rising edge of wkp3 pin input is detected 2 wpeg2 0 r/w wkp2 edge select 0: falling edge of wkp2 pin input is detected 1: rising edge of wkp2 pin input is detected 1 wpeg1 0 r/w wkp1edge select 0: falling edge of wkp1 pin input is detected 1: rising edge of wkp1 pin input is detected 0 wpeg0 0 r/w wkp0 edge select 0: falling edge of wkp0 pin input is detected 1: rising edge of wkp0 pin input is detected
section 3 exception handling rev. 6.00 mar. 24, 2006 page 55 of 412 rej09b0142-0600 3.2.3 interrupt enable register 1 (ienr1) ienr1 enables direct transition inte rrupts, timer a overflow interrupts, and external pin interrupts. bit bit name initial value r/w description 7 iendt 0 r/w direct transfer interrupt enable when this bit is set to 1, direct transition interrupt requests are enabled. 6 ienta 0 r/w timer a interrupt enable when this bit is set to 1, timer a overflow interrupt requests are enabled. 5 ienwp 0 r/w wakeup interrupt enable this bit is an enable bit, which is common to the pins wkp5 to wkp0 . when the bit is set to 1, interrupt requests are enabled. 4 ? 1 ? reserved this bit is always read as 1. 3 ien3 0 r/w irq3 interrupt enable when this bit is set to 1, interrupt requests of the irq3 pin are enabled. 2 ien2 0 r/w irq2 interrupt enable when this bit is set to 1, interrupt requests of the irq2 pin are enabled. 1 ien1 0 r/w irq1 interrupt enable when this bit is set to 1, interrupt requests of the irq1 pin are enabled. 0 ien0 0 r/w irq0 interrupt enable when this bit is set to 1, interrupt requests of the irq0 pin are enabled. when disabling interrupts by clearing bits in an in terrupt enable register, or when clearing bits in an interrupt flag register, always do so while interrupts are masked (i = 1). if the above clear operations are performed while i = 0, and as a resu lt a conflict arises between the clear instruction and an interrupt request, exception handling for the interrupt will be executed after the clear instruction has been executed.
section 3 exception handling rev. 6.00 mar. 24, 2006 page 56 of 412 rej09b0142-0600 3.2.4 interrupt flag register 1 (irr1) irr1 is a status flag register for direct tran sition interrupts, timer a overflow interrupts, and irq3 to irq0 interrupt requests. bit bit name initial value r/w description 7 irrdt 0 r/w direct transfer interrupt request flag [setting condition] when a direct transfer is made by executing a sleep instruction while dton in syscr2 is set to 1. [clearing condition] when irrdt is cleared by writing 0 6 irrta 0 r/w timer a interrupt request flag [setting condition] when the timer a counter value overflows [clearing condition] when irrta is cleared by writing 0 5 4 ? ? 1 1 ? ? reserved these bits are always read as 1. 3 irri3 0 r/w irq3 interrupt request flag [setting condition] when irq3 pin is designated for interrupt input and the designated signal edge is detected. [clearing condition] when irri3 is cleared by writing 0 2 irri2 0 r/w irq2 interrupt request flag [setting condition] when irq2 pin is designated for interrupt input and the designated signal edge is detected. [clearing condition] when irri2 is cleared by writing 0 1 irri1 0 r/w irq1 interrupt request flag [setting condition] when irq1 pin is designated for interrupt input and the designated signal edge is detected. [clearing condition] when irri1 is cleared by writing 0
section 3 exception handling rev. 6.00 mar. 24, 2006 page 57 of 412 rej09b0142-0600 bit bit name initial value r/w description 0 irrl0 0 r/w irq0 interrupt request flag [setting condition] when irq0 pin is designated for interrupt input and the designated signal edge is detected. [clearing condition] when irri0 is cleared by writing 0 3.2.5 wakeup interrupt flag register (iwpr) iwpr is a status flag register for wkp5 to wkp0 interrupt requests. bit bit name initial value r/w description 7 6 ? ? 1 1 ? ? reserved these bits are always read as 1. 5 iwpf5 0 r/w wkp5 interrupt request flag [setting condition] when wkp5 pin is designated for interrupt input and the designated signal edge is detected. [clearing condition] when iwpf5 is cleared by writing 0. 4 iwpf4 0 r/w wkp4 interrupt request flag [setting condition] when wkp4 pin is designated for interrupt input and the designated signal edge is detected. [clearing condition] when iwpf4 is cleared by writing 0. 3 iwpf3 0 r/w wkp3 interrupt request flag [setting condition] when wkp3 pin is designated for interrupt input and the designated signal edge is detected. [clearing condition] when iwpf3 is cleared by writing 0.
section 3 exception handling rev. 6.00 mar. 24, 2006 page 58 of 412 rej09b0142-0600 bit bit name initial value r/w description 2 iwpf2 0 r/w wkp2 interrupt request flag [setting condition] when wkp2 pin is designated for interrupt input and the designated signal edge is detected. [clearing condition] when iwpf2 is cleared by writing 0. 1 iwpf1 0 r/w wkp1 interrupt request flag [setting condition] when wkp1 pin is designated for interrupt input and the designated signal edge is detected. [clearing condition] when iwpf1 is cleared by writing 0. 0 iwpf0 0 r/w wkp0 interrupt request flag [setting condition] when wkp0 pin is designated for interrupt input and the designated signal edge is detected. [clearing condition] when iwpf0 is cleared by writing 0.
section 3 exception handling rev. 6.00 mar. 24, 2006 page 59 of 412 rej09b0142-0600 3.3 reset exception handling when the res pin goes low, all processing halts and this lsi enters the reset. the internal state of the cpu and the registers of the on-chip peripheral modules are initialized by the reset. to ensure that this lsi is reset at power-up, hold the res pin low until the clock pulse generator output stabilizes. to reset the chip during operation, hold the res pin low for at least 10 system clock cycles. when the res pin goes high after bei ng held low for the necessary time, this lsi starts reset exception handling. the reset exception handling sequence is shown in figure 3.1. the reset exception handling sequence is as follows: 1. set the i bit in the condition code register (ccr) to 1. 2. the cpu generates a reset exception handling vector address (from h'0000 to h'0001), the data in that address is sent to the program counter (pc) as the start address, and program execution starts from that address. 3.4 interrupt exception handling 3.4.1 external interrupts there are external interrupts, nmi, irq3 to irq0, and wkp5 to wkp0. (1) nmi interrupt nmi interrupt is requested by input signal edge to pin nmi . this interrupt is detected by either rising edge sensing or falling edge sensing, depending on the setting of bit nmieg in iegr1. nmi is the highest-priority interrupt, and can always be accepted without depending on the i bit value in ccr. (2) irq3 to irq0 interrupts irq3 to irq0 interrupts are requested by input signals to pins irq3 to irq0 . these four interrupts are given different vector addresses, and are detected indi vidually by either rising edge sensing or falling edge sensing, depending on the settings of bits ieg3 to ieg0 in iegr1. when pins irq3 to irq0 are designated for interrupt input in pmr1 and the designated signal edge is input, the corresponding bit in irr1 is set to 1, requesting the cpu of an interrupt. when irq3 to irq0 interrupt is accepted, the i bit is se t to 1 in ccr. these interrupts can be masked by setting bits ien3 to ien0 in ienr1.
section 3 exception handling rev. 6.00 mar. 24, 2006 page 60 of 412 rej09b0142-0600 (3) wkp5 to wkp0 interrupts wkp5 to wkp0 interrupts are requested by input signals to pins wkp 5 to wkp 0. these six interrupts have the same vector addresses, and are detected individually by either rising edge sensing or falling edge sensing, depending on the settings of bits wpeg5 to wpeg0 in iegr2. when pins wkp5 to wkp0 are designated for interrupt input in pmr5 and the designated signal edge is input, the corresponding bit in iwpr is se t to 1, requesting the cpu of an interrupt. these interrupts can be masked by setting bit ienwp in ienr1. vector fetch internal address bus internal read signal internal write signal internal data bus (16 bits) res internal processing initial program instruction prefetch (1) reset exception handling vector address (h'0000) (2) program start address (3) initial program instruction (2) (3) (2) (1) reset cleared figure 3.1 reset sequence
section 3 exception handling rev. 6.00 mar. 24, 2006 page 61 of 412 rej09b0142-0600 3.4.2 internal interrupts each on-chip peripheral module has a flag to show the interrupt request status and the enable bit to enable or disable the interrupt. for timer a interrupt requests and direct transfer interrupt requests generated by execution of a sleep instruction, this function is included in irr1 and ienr1. when an on-chip peripheral module requests an interrupt, the correspon ding interrupt request status flag is set to 1, requesting the cpu of an interrupt. when this inte rrupt is accepted, the i bit is set to 1 in ccr. these interrupts can be masked by writing 0 to clear the corresponding enable bit. 3.4.3 interrupt handling sequence interrupts are controlled by an interrupt controller. interrupt operation is described as follows. 1. if an interrupt occurs while the nmi or interrupt enable bit is set to 1, an interrupt request signal is sent to the interrupt controller. 2. when multiple interrupt requests are generated, the interrupt controller requests to the cpu for the interrupt handling with the highest priority at that time according to table 3.1. other interrupt requests are held pending. 3. the cpu accepts the nmi and address break wi thout depending on the i bit value. other interrupt requests are accepted, if the i bit is clear ed to 0 in ccr; if the i bit is set to 1, the interrupt request is held pending. 4. if the cpu accepts the interrupt after proces sing of the current instruction is completed, interrupt exception handling will begin. first, both pc and ccr are pushed onto the stack. the state of the stack at this time is shown in figure 3.2. the pc value pushed onto the stack is the address of the first instruction to be exec uted upon return from interrupt handling. 5. then, the i bit of ccr is set to 1, masking further interrupts excluding the nmi and address break. upon return from interrupt handling, the values of i bit and other bits in ccr will be restored and returned to the values prior to the start of interrupt exception handling. 6. next, the cpu generates the vector addres s corresponding to th e accepted interrupt, and transfers the address to pc as a start address of the interr upt handling-routine. then a program starts executing from the address indicated in pc. figure 3.3 shows a typical interrupt sequence where the program area is in the on-chip rom and the stack area is in the on-chip ram.
section 3 exception handling rev. 6.00 mar. 24, 2006 page 62 of 412 rej09b0142-0600 pc and ccr saved to stack sp (r7) sp ? 1 sp ? 2 sp ? 3 sp ? 4 stack area sp + 4 sp + 3 sp + 2 sp + 1 sp (r7) even address prior to start of interrupt exception handling after completion of interrupt exception handling [legend] pc h : pc l : ccr: sp: upper 8 bits of program counter (pc) lower 8 bits of program counter (pc) condition code register stack pointer notes: ccr ccr * 3 pch pcl 1. 2. pc shows the address of the first instruction to be executed upon return from the interrupt handling routine. register contents must always be saved and restored by word length, starting from an even-numbered address. 3. ignored when returning from the interrupt handling routine. figure 3.2 stack status after exception handling 3.4.4 interrupt response time table 3.2 shows the number of wait states after an interrupt request flag is set until the first instruction of the interrupt handling-routine is executed. table 3.2 interrupt wait states item states total waiting time for completion of executing instruction * 1 to 23 15 to 37 saving of pc and ccr to stack 4 vector fetch 2 instruction fetch 4 internal processing 4 note: * not including eepmov instruction.
section 3 exception handling rev. 6.00 mar. 24, 2006 page 63 of 412 rej09b0142-0600 vector fetch internal address bus internal read signal internal write signal (2) internal data bus (16 bits) interrupt request signal (9) (1) internal processing prefetch instruction of interrupt-handling routine (1) instruction prefetch address (instruction is not executed. address is saved as pc contents, becoming return address.) (2)(4) instruction code (not executed) (3) instruction prefetch address (instruction is not executed.) (5) sp ? 2 (6) sp ? 4 (7) ccr (8) vector address (9) starting address of interrupt-handling routine (contents of vector) (10) first instruction of interrupt-handling routine (3) (9) (8) (6) (5) (4) (1) (7) (10) stack access internal processing instruction prefetch interrupt level decision and wait for end of instruction interrupt is accepted figure 3.3 interrupt sequence
section 3 exception handling rev. 6.00 mar. 24, 2006 page 64 of 412 rej09b0142-0600 3.5 usage notes 3.5.1 interrupts after reset if an interrupt is accepted after a reset and before the stack pointer (sp) is initialized, the pc and ccr will not be saved correctly, leading to a program crash. to prevent this, all interrupt requests, including nmi, are disabled immediately after a re set. since the first instruction of a program is always executed immediatel y after the reset state ends, make sure that this instruction initializes the stack pointer (example: mov.w #xx: 16, sp). 3.5.2 notes on stack area use when word data is accessed the leas t significant bit of th e address is regarded as 0. access to the stack always takes place in word size, so the st ack pointer (sp: r7) shoul d never indicate an odd address. use push rn (mov.w rn, @?sp) or po p rn (mov.w @sp+, rn) to save or restore register values. 3.5.3 notes on rewriting port mode registers when a port mode register is rewritten to swit ch the functions of external interrupt pins, irq3 to irq0 , and wkp5 to wkp0 , the interrupt request flag may be set to 1. figure 3.4 shows a port mode register setting and interrupt request flag clearing procedure. when switching a pin function, mask the interrupt before setting the bit in the port mode register. after accessing the port mode register, execute at l east one instruction (e.g., nop), then clear the interrupt request flag from 1 to 0.
section 3 exception handling rev. 6.00 mar. 24, 2006 page 65 of 412 rej09b0142-0600 ccr i bit 1 set port mode register bit execute nop instruction interrupts masked. (another possibility is to disable the relevant interrupt in interrupt enable register 1.) after setting the port mode register bit, first execute at least one instruction (e.g., nop), then clear the interrupt request flag to 0 interrupt mask cleared clear interrupt request flag to 0 ccr i bit 0 figure 3.4 port mode register setting and interrupt request flag clearing procedure
section 3 exception handling rev. 6.00 mar. 24, 2006 page 66 of 412 rej09b0142-0600
section 4 address break rev. 6.00 mar. 24, 2006 page 67 of 412 rej09b0142-0600 section 4 address break the address break simplifies on-board program debugg ing. it requests an address break interrupt when the set break condition is satisfied. the interr upt request is not affected by the i bit of ccr. break conditions that can be set include instruction execution at a specific address and a combination of access and data at a specific addr ess. with the address break function, the execution start point of a program containing a bug is detected and execution is branched to the correcting program. figure 4.1 shows a block diagram of the address break. barh barl bdrh bdrl abrkcr abrksr internal address bus comparator interrupt generation control circuit internal data bus comparator interrupt [legend] barh, barl: break address register bdrh, bdrl: break data register abrkcr: address break control register abrksr: address break status register figure 4.1 block diagram of address break
section 4 address break rev. 6.00 mar. 24, 2006 page 68 of 412 rej09b0142-0600 4.1 register descriptions address break has the following registers. ? ? ? ? 7 rtinte 1 r/w rte interrupt enable when this bit is 0, the interrupt immediately after executing rte is masked and then one instruction must be executed. when this bit is 1, the interrupt is not masked. 6 5 csel1 csel0 0 0 r/w r/w condition select 1 and 0 these bits set address break conditions. 00: instruction execution cycle 01: cpu data read cycle 10: cpu data write cycle 11: cpu data read/write cycle 4 3 2 acmp2 acmp1 acmp0 0 0 0 r/w r/w r/w address compare condition select 2 to 0 these bits comparison condition between the address set in bar and the internal address bus. 000: compares 16-bit addresses 001: compares upper 12-bit addresses 010: compares upper 8-bit addresses 011: compares upper 4-bit addresses 1xx: reserved (setting prohibited)
section 4 address break rev. 6.00 mar. 24, 2006 page 69 of 412 rej09b0142-0600 bit bit name initial value r/w description 1 0 dcmp1 dcmp0 0 0 r/w r/w data compare condition select 1 and 0 these bits set the comparison condition between the data set in bdr and the internal data bus. 00: no data comparison 01: compares lower 8-bit data between bdrl and data bus 10: compares upper 8-bit data between bdrh and data bus 11: compares 16-bit data between bdr and data bus [legend] x: don't care. when an address break is set in the data read cy cle or data write cycle, the data bus used will depend on the combination of the byte/word access and address. table 4.1 shows the access and data bus used. when an i/o register space with an 8-bit data bus width is accessed in word size, a byte access is generated twice. for details on da ta widths of each regi ster, see section 19.1, register addr e sses (address order). table 4.1 access and data bus used word access byte access even address odd address even address odd address rom space upper 8 bits lower 8 bits upper 8 bits upper 8 bits ram space upper 8 bits lower 8 bits upper 8 bits upper 8 bits i/o register with 8-bit data bus width upper 8 bits upper 8 bits upper 8 bits upper 8 bits i/o register with 16- bit data bus width upper 8 bits lower 8 bits ? ?
section 4 address break rev. 6.00 mar. 24, 2006 page 70 of 412 rej09b0142-0600 4.1.2 address break status register (abrksr) abrksr consists of the address break interrupt flag and the address break interrupt enable bit. bit bit name initial value r/w description 7 abif 0 r/w address break interrupt flag [setting condition] when the condition set in abrkcr is satisfied [clearing condition] when 0 is written after abif=1 is read 6 abie 0 r/w address break interrupt enable when this bit is 1, an address break interrupt request is enabled. 5 to 0 ? all 1 ? reserved these bits are always read as 1. 4.1.3 break address re gisters (barh, barl) barh and barl are 16-bit read/w rite registers that set the address for generating an address break interrupt. when setting the address break condition to the instruction execution cycle, set the first byte address of the instruction. th e initial value of this register is h'ffff. 4.1.4 break data registers (bdrh, bdrl) bdrh and bdrl are 16-bit read/w rite registers that set the data for generating an address break interrupt. bdrh is compared with the upper 8-bit data bus. bdrl is compared with the lower 8- bit data bus. when memory or registers are accessed by byte, the u pper 8-bit data bus is used for even and odd addresses in the data transmission. therefore, comparison data must be set in bdrh for byte access. fo r word access, the data bus used depe nds on the address. see section 4.1.1, address break control register (abrkcr), for details. the initial value of this register is undefined.
section 4 address break rev. 6.00 mar. 24, 2006 page 71 of 412 rej09b0142-0600 4.2 operation when the abif and abie bits in abrksr are set to 1, the address break function generates an interrupt request to the cpu. the abif bit in abrksr is set to 1 by the combination of the address set in bar, the data set in bdr, and th e conditions set in abrkcr. when the interrupt request is accepted, interr upt exception handling starts after the instruction being executed ends. the address break interrupt is not masked because of the i bit in ccr of the cpu. figures 4.2 show the operation examples of the address break interrupt setting. nop instruc- tion prefetch register setting abrkcr = h'80 bar = h'025a program 0258 025a 025c 0260 0262 : * nop nop mov.w @h'025a,r0 nop nop : 0258 address bus interrupt request 025a 025c 025e sp-2 sp-4 nop instruc- tion prefetch mov instruc- tion 1 prefetch mov instruc- tion 2 prefetch internal processing stack save interrupt acceptance underline indicates the address to be stacked. when the address break is specified in instruction execution cycle figure 4.2 address break in terrupt operation example (1)
section 4 address break rev. 6.00 mar. 24, 2006 page 72 of 412 rej09b0142-0600 mov instruc- tion 1 prefetch register setting abrkcr = h'a0 bar = h'025a program 0258 025a 025c 0260 0262 : * nop nop mov.w @h'025a,r0 nop nop : 025c address bus interrupt request 025e 0260 025a 0262 0264 sp-2 mov instruc- tion 2 prefetch nop instruc- tion prefetch mov instruc- tion execution next instru- ction prefetch internal processing stack save nop instruc- tion prefetch interrupt acceptance underline indicates the address to be stacked. when the address break is specified in the data read cycle figure 4.2 address break in terrupt operation example (2)
section 4 address break rev. 6.00 mar. 24, 2006 page 73 of 412 rej09b0142-0600 4.3 usage notes when an address break is set to an instruction after a conditional branch instruction, and the instruction set when the condition of the branch inst ruction is not satisfied is executed (see figure 4.3), note that an address break interrupt request is not generated. therefore an address break must not be set to the instruction after a conditional branch instruction. 0134 address bus address break interrupt request 0136 102a 0138 [register setting] bne instruction prefetch nop instruction prefetch mov instruction prefetch nop instruction prefetch abrkcr = h'80 bar = h'0136 012a mov.b . . . : : 0134 bne * 0136 nop 0138 nop : : [program] figure 4.3 operation when condition is not satisfied in branch instruction
section 4 address break rev. 6.00 mar. 24, 2006 page 74 of 412 rej09b0142-0600 when another interrupt request is accepted before an instruction to which an address break is set is executed, exception handlin g of an address break interrupt is not executed. however, the abif bit is set to 1 (see figure 4.4). therefore the abif b it must be read during exception handling of an address break interrupt. 0142 0144 0146 * mov.b #h'23,r1h mov.b #h'45,r1h mov.b #h'67,r1h 0142 0144 0146 sp-2 sp-4 001c 0900 abif [register setting] external interrupt underlined indicates the address to be stacked. abrkcr = h'80 bar = h'0144 001c 0900 : : [program] mov instruction prefetch mov instruction prefetch mov instruction prefetch stack save vector fetch internal processing external interrupt acceptance internal processing address bus external interrupt acceptance address break interrupt request figure 4.4 operation when another interrupt is accepted at address break setting instruction
section 4 address break rev. 6.00 mar. 24, 2006 page 75 of 412 rej09b0142-0600 when an address break is set to an instruction as a branch destination of a conditional branch instruction, the instruction set when the condition of the branch instruction is not satisfied is not executed, and an address break is generated. ther efore an address break mu st not be set to the instruction as a branch destination of a conditional branch instruction. bne instruction prefetch nop instruction prefetch mov instruction prefetch nop instruction prefetch [register setting] ? adbrkcr = h'80 ? bar = h'0150 [program] 0134 0136 0138 0150 * bne nop nop mov.b 0134 address bus address break interrupt request 0136 0150 0138 interrupt acceptance . . . figure 4.5 operation when th e instruction set is not executed and does not branch due to conditions not being satisfied
section 4 address break rev. 6.00 mar. 24, 2006 page 76 of 412 rej09b0142-0600
section 5 clock pulse generators rev. 6.00 mar. 24, 2006 page 77 of 412 rej09b0142-0600 section 5 clock pulse generators clock oscillator circuitry (cpg: clock pulse generator) is provided on-chip, including both a system clock pulse generator and a subclock puls e generator. the system clock pulse generator consists of a system clock oscillator, a duty co rrection circuit, and system clock dividers. the subclock pulse generator consists of a subclock oscillator circuit and a subclock divider. figure 5.1 shows a block diagram of the clock pulse generators. system clock oscillator subclock oscillator subclock divider duty correction circuit system clock divider prescaler s (13 bits) prescaler w (5 bits) osc 1 osc 2 x 1 x 2 system clock pulse generator osc (f osc ) osc (f osc ) w (f w ) w /2 w /4 sub /2 to /8192 w /8 osc /8 osc osc /16 osc /32 osc /64 w /8 to w /128 subclock pulse generator figure 5.1 block diagram of clock pulse generators the basic clock signals that drive the cpu and on-chip peripheral modules are
section 5 clock pulse generators rev. 6.00 mar. 24, 2006 page 78 of 412 rej09b0142-0600 5.1 system clock generator clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic resonator, or by providing external clock input. figure 5.2 shows a block diagram of the system clock generator. lpm lpm: low-power mode (standby mode, subactive mode, subsleep mode) 2 1 osc osc figure 5.2 block diagram of system clock generator 5.1.1 connecting crystal resonator figure 5.3 shows a typical method of connecting a crystal resonator. an at-cut parallel-resonance crystal resonator should be used. figure 5.4 shows the equivalent circuit of a crystal resonator. a resonator having the characteristics given in table 5.1 should be used. 1 2 c 1 c 2 osc osc c 1 = c 2 = 12 pf 20% note: capacitances are reference values. figure 5.3 typical connect ion to crystal resonator c s c 0 r s osc 1 osc 2 l s figure 5.4 equivalent circuit of crystal resonator
section 5 clock pulse generators rev. 6.00 mar. 24, 2006 page 79 of 412 rej09b0142-0600 table 5.1 crystal resonator parameters frequency (mhz) 2 4 8 10 16 r s (max) 500 ? 120 ? 80 ? 60 ? 50 ? c 0 (max) 7 pf 7 pf 7 pf 7 pf 7 pf 5.1.2 connecting ceramic resonator figure 5.5 shows a typical method of connecting a ceramic resonator. osc 1 osc 2 c 1 c 2 c 1 = 30 pf 10% c 2 = 30 pf 10% note: capacitances are reference values. figure 5.5 typical connect ion to cerami c resonator 5.1.3 external clock input method connect an external clock signal to pin osc 1 , and leave pin osc 2 open. figure 5.6 shows a typical connection. the duty cycle of the external clock sign al must be 45 to 55%. osc 1 external clock input osc 2 open figure 5.6 example of external clock input
section 5 clock pulse generators rev. 6.00 mar. 24, 2006 page 80 of 412 rej09b0142-0600 5.2 subclock generator figure 5.7 shows a block diagram of the subclock generator. note : resistance is a reference value. 2 8m 1 x x figure 5.7 block diagram of subclock generator 5.2.1 connecting 32.768-khz crystal resonator clock pulses can be supplied to the subclock divider by connecting a 32.768-khz crystal resonator, as shown in figure 5.8. figure 5.9 shows the equivalent circuit of the 32.768-khz crystal resonator. note: capacitances are reference values. x x c 1 c 2 1 2 c 1 = c 2 = 15 pf (typ.) figure 5.8 typical connection to 32.768-khz crystal resonator x 1 x 2 l s c s c o c o = 1.5 pf (typ.) r s = 14 k (typ.) f w = 32.768 khz r s note: constants are reference values. figure 5.9 equivalent circuit of 32.768-khz crystal resonator
section 5 clock pulse generators rev. 6.00 mar. 24, 2006 page 81 of 412 rej09b0142-0600 5.2.2 pin connection when not using subclock when the subclock is not used, connect pin x 1 to v cl or v ss and leave pin x 2 open, as shown in figure 5.10. x 1 v cl or v ss x 2 open figure 5.10 pin connection when not using subclock 5.3 prescalers 5.3.1 prescaler s prescaler s is a 13-bit counter using the system clock (
section 5 clock pulse generators rev. 6.00 mar. 24, 2006 page 82 of 412 rej09b0142-0600 5.4 usage notes 5.4.1 note on resonators resonator characteristics are closely related to boar d design and should be carefully evaluated by the user, referring to the examples shown in this section. resonator circuit constants will differ depending on the resonator element, stray capac itance in its interconnecting circuit, and other factors. suitable constants should be determined in consultation with the resonator element manufacturer. design the circuit so that the resonator element never receives voltages exceeding its maximum rating. 5.4.2 notes on board design when using a crystal resonator (ceramic resonator) , place the resonator and it s load capacitors as close as possible to the osc 1 and osc 2 pins. other signal lines should be routed away from the resonator circuit to prevent induc tion from interfering with correct oscillation (see figure 5.11). osc 1 osc 2 c 1 c 2 signal a signal b avoid figure 5.11 example of incorrect board design
section 6 power-down modes rev. 6.00 mar. 24, 2006 page 83 of 412 rej09b0142-0600 section 6 power-down modes this lsi has six modes of operation after a reset. these include a normal active mode and four power-down modes, in which power consumption is significantly reduced. module standby mode reduces power consumption by selectively halting on-chip module functions. ? ? ? ? ? ?
section 6 power-down modes rev. 6.00 mar. 24, 2006 page 84 of 412 rej09b0142-0600 6.1 register descriptions the registers related to power-down modes are listed below. ? ? ? 6.1.1 system control register 1 (syscr1) syscr1 controls the power-down modes, as well as syscr2. bit bit name initial value r/w description 7 ssby 0 r/w software standby this bit selects the mode to transit after the execution of the sleep instruction. 0: a transition is made to sleep mode or subsleep mode. 1: a transition is made to standby mode. for details, see table 6.2. 6 5 4 sts2 sts1 sts0 0 0 0 r/w r/w r/w standby timer select 2 to 0 these bits designate the time the cpu and peripheral modules wait for stable clock operation after exiting from standby mode, subactiv e mode, or subsleep mode to active mode or sleep mode due to an interrupt. the designation should be made according to the clock frequency so that the waiting time is at least 6.5 ms. the relationship between t he specified value and the number of wait states is shown in table 6.1. when an external clock is to be used, the minimum value (sts2 = sts1 = sts0 = 1) is recommended.
section 6 power-down modes rev. 6.00 mar. 24, 2006 page 85 of 412 rej09b0142-0600 bit bit name initial value r/w description 3 nesel 0 r/w noise eliminat ion sampling frequency select the subclock pulse generat or generates the watch clock signal ( w ) and the system clock pulse generator generates the oscillator clock ( osc ). this bit selects the sampling frequency of the oscillator clock when the watch clock signal ( w ) is sampled. when osc = 4 to 16 mhz, clear nesel to 0. 0: sampling rate is osc /16 1: sampling rate is osc /4 2 1 0 ? ? ? 0 0 0 ? ? ? reserved these bits are always read as 0. table 6.1 operating frequency and waiting time sts2 sts1 sts0 waiting time 16 mhz 10 mhz 8 mhz 4 mhz 2 mhz 1 mhz 0.5 mhz 0 0 0 8,192 states 0.5 0.8 1.0 2.0 4.1 8.1 16.4 1 16,384 states 1.0 1.6 2.0 4.1 8.2 16.4 32.8 1 0 32,768 states 2.0 3.3 4.1 8.2 16.4 32.8 65.5 1 65,536 states 4.1 6.6 8.2 16.4 32.8 65.5 131.1 1 0 0 131,072 states 8.2 13.1 16.4 32.8 65.5 131.1 262.1 1 1,024 states 0.06 0.10 0.13 0.26 0.51 1.02 2.05 1 0 128 states 0.00 0.01 0.02 0.03 0.06 0.13 0.26 1 16 states 0.00 0.00 0.00 0.00 0.01 0.02 0.03 note: time unit is ms.
section 6 power-down modes rev. 6.00 mar. 24, 2006 page 86 of 412 rej09b0142-0600 6.1.2 system control register 2 (syscr2) syscr2 controls the power-down modes, as well as syscr1. bit bit name initial value r/w description 7 6 5 smsel lson dton 0 0 0 r/w r/w r/w sleep mode selection low speed on flag direct transfer on flag these bits select the mode to transit after the execution of a sleep instruction, as well as bit ssby of syscr1. for details, see table 6.2. 4 3 2 ma2 ma1 ma0 0 0 0 r/w r/w r/w active mode clock select 2 to 0 these bits select the operating clock frequency in active and sleep modes. the operating clock frequency changes to the set frequency after the sleep instruction is executed. 0xx: osc 100: osc /8 101: osc /16 110: osc /32 111: osc /64 1 0 sa1 sa0 0 0 r/w r/w subactive mode clock select 1 and 0 these bits select the operating clock frequency in subactive and subsleep modes. the operating clock frequency changes to the set frequency after the sleep instruction is executed. 00: w /8 01: w /4 1x: w /2 [legend] x: don't care.
section 6 power-down modes rev. 6.00 mar. 24, 2006 page 87 of 412 rej09b0142-0600 6.1.3 module standby control register 1 (mstcr1) mstcr1 allows the on-chip peripheral module s to enter a standby state in module units. bit bit name initial value r/w description 7 ? 0 ? reserved this bit is always read as 0. 6 mstiic 0 r/w iic module standby iic enters standby mode when this bit is set to 1 5 msts3 0 r/w sci3 module standby sci3 enters standby mode when this bit is set to 1 4 mstad 0 r/w a/d converter module standby a/d converter enters standby mode when this bit is set to 1 3 mstwd 0 r/w watchdog timer module standby watchdog timer enters standby mode when this bit is set to 1.when the internal oscillator is selected for the watchdog timer clock, the watchdog timer operates regardless of the setting of this bit 2 msttw 0 r/w timer w module standby timer w enters standby mode when this bit is set to 1 1 msttv 0 r/w timer v module standby timer v enters standby mode when this bit is set to 1 0 mstta 0 r/w timer a module standby timer a enters standby mode when this bit is set to 1
section 6 power-down modes rev. 6.00 mar. 24, 2006 page 88 of 412 rej09b0142-0600 6.2 mode transitions and states of lsi figure 6.1 shows the possible transitions among these operating modes. a transition is made from the program execution state to the program halt state of the program by executing a sleep instruction. interrupts allow for returning from the program halt state to the program execution state of the program. a direct transition between active mode and subactive mode, which are both program execution states, can be made without halting the program. the operating frequency can also be changed in the same modes by making a transition directly from active mode to active mode, and from subactive mode to subactive mode. res input enables transitions from a mode to the reset state. table 6.2 shows the transition conditions of each mode after the sleep instruction is executed and a mode to return by an interrupt. table 6.3 shows the internal states of the lsi in each mode. reset state standby mode active mode sleep mode subsleep mode subactive mode program halt state program execution state program halt state sleep instruction sleep instruction interrupt direct transition interrupt direct transition interrupt notes: 1. to make a transition to another mode by an interrupt, make sure interrupt handling is after the interrupt is accepted. 2. details on the mode transition conditions are given in table 6.2. sleep instruction direct transition interrupt direct transition interrupt interrupt sleep instruction interrupt interrupt sleep instruction interrupt sleep instruction figure 6.1 mode transition diagram
section 6 power-down modes rev. 6.00 mar. 24, 2006 page 89 of 412 rej09b0142-0600 table 6.2 transition mode after sleep inst ruction execution and interrupt handling dton ssby smsel lson transition mode after sleep instruction execution transition mode due to interrupt 0 0 0 0 sleep mode active mode 1 subactive mode 1 0 subsleep mode active mode 1 subactive mode 1 x x standby mode active mode 1 x 0 * 0 active mode (direct transition) ? x x 1 subactive mode (direct transition) ? [legend] x: don't care. note: * when a state transition is performed while smsel is 1, timer v, sci3, and the a/d converter are reset, and all registers are set to their initial values. to use these functions after entering active mode, reset the registers.
section 6 power-down modes rev. 6.00 mar. 24, 2006 page 90 of 412 rej09b0142-0600 table 6.3 internal state in each operating mode function active mode sleep mode subactive mode subsleep mode standby mode system clock oscillator functioning functioning halted halted halted subclock oscillator functioning functi oning functioning functioning functioning instructions functioning halted functioning halted halted cpu operations registers functioning retained functioning retained retained ram functioning retained f unctioning retained retained io ports functioning retained functioning retained register contents are retained, but output is the high- impedance state. irq3 to irq0 functioning functioni ng functioning functioning functioning external interrupts wkp5 to wkp0 functioning functioning functi oning functioning functioning timer a functioning functioning functi oning if the timekeeping time-base function is selected, and retained if not selected timer v functioning functioning reset reset reset timer w functioning functioning retained (if internal clock is selected as a count clock, the counter is incremented by a subclock * ) retained watchdog timer functioning functioning retained (functioning if the internal oscillator is selected as a count clock * ) sci3 functioning functioning reset reset reset iic functioning functioning retained * retained retained peripheral functions a/d converter functioning functioning reset reset reset note: * registers can be read or written in subactive mode.
section 6 power-down modes rev. 6.00 mar. 24, 2006 page 91 of 412 rej09b0142-0600 6.2.1 sleep mode in sleep mode, cpu operation is halted but the on-chip peripheral modules function at the clock frequency set by the ma2, ma1, and ma0 bits in syscr2. cpu register contents are retained. when an interrupt is requested, sleep mode is cleared and interrupt exception handling starts. sleep mode is not cleared if the i bit of the co ndition code register (ccr) is set to 1 or the requested interrupt is disabled in the interrupt enable register. after sleep mode is cleared, a transition is made to active mode when the lson b it in syscr2 is 0, and a transition is made to subactive mode when the bit is 1. when the res pin goes low, the cpu goes into the reset state and sleep mode is cleared. 6.2.2 standby mode in standby mode, the clock pulse generator stops, so the cpu and on-chip peripheral modules stop functioning. however, as long as the rated voltage is supplied, the contents of cpu registers, on- chip ram, and some on-chip peripheral module registers are retained. on-chip ram contents will be retained as long as the voltage set by the ram data retention voltage is provided. the i/o ports go to the high-impedance state. standby mode is cleared by an in terrupt. when an interrupt is requested, the system clock pulse generator starts. after the time set in bits st s2?sts0 in syscr1 has elapsed, and interrupt exception handling starts. standby mode is not cleared if the i bit of ccr is set to 1 or the requested interrupt is disabled in the interrupt enable register. when the res pin goes low, the system clock pulse generator starts. since system clock signals are supplied to the entire ch ip as soon as the system clock puls e generator starts functioning, the res pin must be kept low until the pulse generator output stabilizes. after the pulse generator output has stabilized, the cpu starts reset exception handling if the res pin is driven high.
section 6 power-down modes rev. 6.00 mar. 24, 2006 page 92 of 412 rej09b0142-0600 6.2.3 subsleep mode in subsleep mode, operation of the cpu and on-chip peripheral modules other than timer a is halted. as long as a required voltage is applied, the contents of cpu registers, the on-chip ram, and some registers of the on-chip peripheral modul es are retained. i/o ports keep the same states as before the transition. subsleep mode is cleared by an in terrupt. when an interrupt is requ ested, subsleep mode is cleared and interrupt exception handling starts. subsleep mode is not cleared if the i bit of ccr is set to 1 or the requested interrupt is disabled in the interrupt enable register. after subsleep mode is cleared, a transition is made to active mode when th e lson bit in syscr2 is 0, and a transition is made to subactive mode when the bit is 1. when the res pin goes low, the system clock pulse generator starts. since system clock signals are supplied to the entire chip as soon as the system clock pu lse generator starts functioning, the res pin must be kept low until the pulse generator output stabilizes. after the pulse generator output has stabilized, the cpu starts reset exception handling if the res pin is driven high. 6.2.4 subactive mode the operating frequency of subactive mode is selected from res pin goes low, the system clock pulse generator starts. since system clock signals are supplied to the entire chip as soon as the system clock pulse genera tor starts functioning, the res pin must be kept low until the pulse generator output stabilizes. after the pulse generator output has stabilized, the cpu starts reset exception handling if the res pin is driven high.
section 6 power-down modes rev. 6.00 mar. 24, 2006 page 93 of 412 rej09b0142-0600 6.3 operating frequency in active mode operation in active mode is clocked at the frequency designated by the ma2, ma1, and ma0 bits in syscr2. the operating frequency changes to the set frequency after sleep instruction execution. 6.4 direct transition the cpu can execute programs in two modes: activ e and subactive mode. a direct transition is a transition between these two modes without stoppi ng program execution. a direct transition can be made by executing a sleep instruction while the dton bit in syscr2 is set to 1. the direct transition also enables operating frequency modi fication in active or subactive mode. after the mode transition, direct transition interrupt exception handling starts. if the direct transition interrupt is disabled in in terrupt enable register 1, a transition is made instead to sleep or subsleep mode. note that if a direct transition is attempted while the i bit in ccr is set to 1, sleep or subsleep mode will be en tered, and the resulting mode cannot be cleared by means of an interrupt. 6.4.1 direct transition from ac tive mode to subactive mode the time from the start of sleep instruction execu tion to the end of interrupt exception handling (the direct transition time) is calculated by equation (1). direct transition time = {(number of s leep instruction execution states) + (number of internal processing states)} example: direct transition time = (2 + 1)
section 6 power-down modes rev. 6.00 mar. 24, 2006 page 94 of 412 rej09b0142-0600 6.4.2 direct transition from su bactive mode to active mode the time from the start of sleep instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (2). direct transition time = {(number of sleep instruction execution states) + (number of internal processing states)} example direct transition time = (2 + 1) tosc: osc clock cycle time tw: watch clock cycle time tcyc: system clock ( 6.5 module standby function the module-standby function can be set to any peripheral module. in module standby mode, the clock supply to modules stops to enter the po wer-down mode. module standby mode enables each on-chip peripheral module to enter the standby st ate by setting a bit that corresponds to each module to 1 and cancels the mode by clearing the bit to 0. 6.6 usage note when subsleep mode is entered by setting the smsel bit to 1 while the subclock is not used (the x 1 pin is fixed), note that active mode cannot be re-entered by using an interrupt. to use a power- down mode while a port is retained, connect the subclock to the x 1 and x 2 pins.
section 7 rom rev. 6.00 mar. 24, 2006 page 95 of 412 rej09b0142-0600 section 7 rom the features of the 32-kbyte flash memory built into the flash memory version are summarized below. ? ? ? ? ? ? ? ? ? ? ? ? ? ?
section 7 rom rev. 6.00 mar. 24, 2006 page 96 of 412 rej09b0142-0600 7.1 block configuration figure 7.1 shows the block configuration of 32-kbyte flash memory. the thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. the flash memory is divided into 1 kbyte h'007f h'0000 h'0001 h'0002 h'00ff h'0080 h'0081 h'0082 h'03ff h'0380 h'0381 h'0382 h'047f h'0400 h'0401 h'0402 h'04ff h'0480 h'0481 h'0481 h'07ff h'0780 h'0781 h'0782 h'087f h'0800 h'0801 h'0802 h'08ff h'0880 h'0881 h'0882 h'0bff h'0b80 h'0b81 h'0b82 h'0c7f h'0c00 h'0c01 h'0c02 h'0cff h'0c80 h'0c81 h'0c82 h'0fff h'0f80 h'0f81 h'0f82 h'107f h'1000 h'1001 h'1002 h'10ff h'1080 h'1081 h'1082 h'7fff h'7f80 h'7f81 h'7f82 programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes 1kbyte erase unit 1kbyte erase unit 1kbyte erase unit 1kbyte erase unit 28 kbytes erase unit figure 7.1 flash memory block configuration
section 7 rom rev. 6.00 mar. 24, 2006 page 97 of 412 rej09b0142-0600 7.2 register descriptions the flash memory has th e following registers. ? ? ? ? ? 7.2.1 flash memory control register 1 (flmcr1) flmcr1 is a register that makes the flash memory change to program mode, program-verify mode, erase mode, or erase-verify mode. for details on register setting, refer to section 7.4, flash memory programming/erasing. bit bit name initial value r/w description 7 ? 0 ? reserved this bit is always read as 0. 6 swe 0 r/w software write enable when this bit is set to 1, flash memory programming/erasing is enabled. when this bit is cleared to 0, other flmcr1 register bits and all ebr1 bits cannot be set. 5 esu 0 r/w erase setup when this bit is set to 1, the flash memory changes to the erase setup state. w hen it is cleared to 0, the erase setup state is cancelled. set this bit to 1 before setting the e bit to 1 in flmcr1. 4 psu 0 r/w program setup when this bit is set to 1, the flash memory changes to the program setup state. w hen it is cleared to 0, the program setup state is cancelled. set this bit to 1 before setting the p bit in flmcr1.
section 7 rom rev. 6.00 mar. 24, 2006 page 98 of 412 rej09b0142-0600 bit bit name initial value r/w description 3 ev 0 r/w erase-verify when this bit is set to 1, the flash memory changes to erase-verify mode. when it is cleared to 0, erase-verify mode is cancelled. 2 pv 0 r/w program-verify when this bit is set to 1, the flash memory changes to program-verify mode. when it is cleared to 0, program-verify mode is cancelled. 1 e 0 r/w erase when this bit is set to 1, and while the swe=1 and esu=1 bits are 1, the flash memory changes to erase mode. when it is cleared to 0, erase mode is cancelled. 0 p 0 r/w program when this bit is set to 1, and while the swe=1 and psu=1 bits are 1, the flash memory changes to program mode. when it is cleared to 0, program mode is cancelled. 7.2.2 flash memory control register 2 (flmcr2) flmcr2 is a register that displa ys the state of flash memory programming/erasing. flmcr2 is a read-only register, and should not be written to. bit bit name initial value r/w description 7 fler 0 r flash memory error indicates that an error has occurred during an operation on flash memory (programming or erasing). when fler is set to 1, flash memory goes to the error- protection state. see section 7.5.3, err o r protection, for details. 6 to 0 ? all 0 ? reserved these bits are always read as 0.
section 7 rom rev. 6.00 mar. 24, 2006 page 99 of 412 rej09b0142-0600 7.2.3 erase block register 1 (ebr1) ebr1 specifies the flash memory er ase area block. ebr1 is initial ized to h'00 when the swe bit in flmcr1 is 0. do not set more than one bit at a time, as this will cause all the bits in ebr1 to be automatically cleared to 0. bit bit name initial value r/w description 7 to 5 ? all 0 ? reserved these bits are always read as 0. 4 eb4 0 r/w when this bit is set to 1, 28 kbytes of h'1000 to h'7fff will be erased. 3 eb3 0 r/w when this bit is set to 1, 1 kbyte of h'0c00 to h'0fff will be erased. 2 eb2 0 r/w when this bit is set to 1, 1 kbyte of h'0800 to h'0bff will be erased. 1 eb1 0 r/w when this bit is set to 1, 1 kbyte of h'0400 to h'07ff will be erased. 0 eb0 0 r/w when this bit is set to 1, 1 kbyte of h'0000 to h'03ff will be erased. 7.2.4 flash memory power control register (flpwcr) flpwcr enables or disables a transition to th e flash memory power-down mode when the lsi switches to subactive mode. there are two modes: mode in which operation of the power supply circuit of flash memory is partly halted in pow er-down mode and flash me mory can be read, and mode in which even if a transition is made to subactive mode, operat ion of the power supply circuit of flash memory is retain ed and flash memory can be read. bit bit name initial value r/w description 7 pdwnd 0 r/w power-down disable when this bit is 0 and a transition is made to subactive mode, the flash memory ent ers the power-down mode. when this bit is 1, the flash memory remains in the normal mode even after a transition is made to subactive mode. 6 to 0 ? all 0 ? reserved these bits are always read as 0.
section 7 rom rev. 6.00 mar. 24, 2006 page 100 of 412 rej09b0142-0600 7.2.5 flash memory enable register (fenr) bit 7 (flshe) in fenr enables or disables the cpu access to the flash memo ry control registers, flmcr1, flmcr2, ebr1, and flpwcr. bit bit name initial value r/w description 7 flshe 0 r/w flash memory control register enable flash memory control registers can be accessed when this bit is set to 1. flash memory control registers cannot be accessed when this bit is set to 0. 6 to 0 ? all 0 ? reserved these bits are always read as 0. 7.3 on-board programming modes there are two modes for programming/erasing of the flash memory; boot mode, which enables on- board programming/erasing, and programmer mode, in which programming/erasing is performed with a prom programmer. on-board programming/erasing can also be performed in user program mode. at reset-start in reset mode, the series of hd64f3664 changes to a mode depending on the test pin settings, nmi pin settings, and input level of each port, as shown in table 7.1. the input level of each pin must be defined four states before the reset ends. when changing to boot mode, the boot program built into this lsi is initiated. the boot program transfers the programming control program from the externally-connected host to on-chip ram via sci3. after erasing the entir e flash memory, the programming control program is executed. this can be used for programming initial values in the on-board state or for a forcible return when programming/erasing can no longer be done in user program mode. in user program mode, individual blocks can be erased and programmed by branching to the user program/erase control program prepared by the user. table 7.1 setting programming modes test nmi p85 pb0 pb1 pb2 lsi state after reset end 0 1 x x x x user mode 0 0 1 x x x boot mode 1 x x 0 0 0 programmer mode [legend] x: don't care.
section 7 rom rev. 6.00 mar. 24, 2006 page 101 of 412 rej09b0142-0600 7.3.1 boot mode table 7.2 shows the boot mode operations between reset end and branching to the programming control program. 1. when boot mode is used, the flash memory programming control program must be prepared in the host beforehand. prepare a programming control program in accordance with the description in section 7.4, flash memory programming/erasing. 2. sci3 should be set to asynchronous mode, and the transfer format as follows: 8-bit data, 1 stop bit, and no parity. 3. when the boot program is initiated, the chip measures the low-level period of asynchronous sci communication data (h'00) transmitted continuously from the host. the chip then calculates the bit rate of transmission from the host, and adjusts the sci3 bit rate to match that of the host. the reset should end with the rxd pin high. the rxd and txd pins should be pulled up on the board if necessary. after the reset is complete, it takes approximately 100 states before the chip is ready to measure the low-level period. 4. after matching the bit rates, the chip transmits one h'00 byte to the host to indicate the completion of bit rate adjustment. the host should confirm that this adjustment end indication (h'00) has been received normally, and transmit on e h'55 byte to the chip. if reception could not be performed normally, initia te boot mode again by a reset. depending on the host's transfer bit rate and system clock frequency of this lsi, there will be a discrepancy between the bit rates of the host and the chip. to oper ate the sci properly, set the host's transfer bit rate and system clock frequency of this lsi within the ranges listed in table 7.3. 5. in boot mode, a part of the on-chip ram area is used by the boot program. the area h'f780 to h'feef is the area to which the programming control program is transferred from the host. the boot program area cannot be used until the execution state in boot mode switches to the programming control program. 6. before branching to the programming control pr ogram, the chip terminat es transfer operations by sci3 (by clearing the re and te bits in scr to 0), however the adjusted bit rate value remains set in brr. therefore, the programmin g control program can still use it for transfer of write data or verify data with the host. the txd pin is high (pcr22 = 1, p22 = 1). the contents of the cpu general registers are undefined immediately after branching to the programming control program. these registers must be initialized at the beginning of the programming control program, as the stack pointer (sp), in particular, is used implicitly in subroutine calls, etc. 7. boot mode can be cleared by a reset. end the reset after driving the reset pin low, waiting at least 20 states, and then setting the test pin and nmi pin. boot mode is also cleared when a wdt overflow occurs. 8. do not change the test pin and nmi pin input levels in boot mode.
section 7 rom rev. 6.00 mar. 24, 2006 page 102 of 412 rej09b0142-0600 table 7.2 boot mode operation communication contents processing contents host operation lsi operation processing contents continuously transmits data h'00 at specified bit rate. branches to boot program at reset-start. boot program initiation h'00, h'00 . . . h'00 h'00 h'55 h'55 reception. transmits data h'55 when data h'00 is received error-free. h'xx transmits number of bytes (n) of programming control program to be transferred as 2-byte data (low-order byte following high-order byte) transmits 1-byte of programming control program (repeated for n times) h'aa reception h'aa reception upper bytes, lower bytes echoback echoback h'aa h'aa branches to programming control program transferred to on-chip ram and starts execution. transmits data h'aa to host when data h'55 is received. checks flash memory data, erases all flash memory blocks in case of written data existing, and transmits data h'aa to host. (if erase could not be done, transmits data h'ff to host and aborts operation.) h'ff boot program erase error item boot mode initiation measures low-level period of receive data h'00. calculates bit rate and sets brr in sci3. transmits data h'00 to host as adjustment end indication. bit rate adjustment echobacks the 2-byte data received to host. echobacks received data to host and also transfers it to ram. (repeated for n times) transfer of number of bytes of programming control program flash memory erase
section 7 rom rev. 6.00 mar. 24, 2006 page 103 of 412 rej09b0142-0600 table 7.3 system clock frequencies for which automatic adjustment of lsi bit rate is possible host bit rate system cloc k frequency range of lsi 19,200 bps 16 mhz 9,600 bps 8 to 16 mhz 4,800 bps 4 to 16 mhz 2,400 bps 2 to 16 mhz 7.3.2 programming/erasing in user program mode on-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program. the user must set branching conditions and provide on-board means of supplying programming data. the flash memory must contain the user program/erase control program or a program that provides the user program/erase control program from external memory. as the flash memory itself cannot be read during programming/erasing, transfer the user program/erase control program to on-chip ram, as in boot mode. figure 7.2 shows a sample procedure for programming/erasing in user program mode. prepare a user program/erase control program in accordance with the description in section 7.4, flash memory programming/erasing. ye s no program/erase? transfer user program/erase control program to ram reset-start branch to user program/erase control program in ram execute user program/erase control program (flash memory rewrite) branch to flash memory application program branch to flash memory application program figure 7.2 programming/erasing flowchart example in user program mode
section 7 rom rev. 6.00 mar. 24, 2006 page 104 of 412 rej09b0142-0600 7.4 flash memory programming/erasing a software method using the cpu is employed to program and erase fl ash memory in the on- board programming modes. depending on the flmcr1 setting, the flash memory operates in one of the following four modes: program mode, program-verify mode, erase mode, and erase-verify mode. the programming control program in boot mode and the user program/erase control program in user program mode use these operating modes in combination to perform programming/erasing. flash memory programming and erasing should be performed in accordance with the descriptions in section 7.4. 1, program/program-veri fy and sect ion 7.4.2, erase/erase-verify, respectively. 7.4.1 program/program-verify when writing data or programs to the flash memory, the program/program-verify flowchart shown in figure 7.3 should be followed. performing programming operations according to this flowchart will enable data or programs to be written to the flash memory without subjecting the chip to voltage stress or sacrificing program data reliability. 1. programming must be done to an empty address. do not reprogram an address to which programming has already been performed. 2. programming should be carried out 128 bytes at a time. a 128-byte data transfer must be performed even if writing fewer than 128 bytes. in this case, h'ff data must be written to the extra addresses. 3. prepare the following data storage areas in ram: a 128-byte programming data area, a 128- byte reprogramming data area, and a 128-byte additional-programming data area. perform reprogramming data computation according to table 7.4, and additional programming data computation according to table 7.5. 4. consecutively transfer 128 bytes of data in byte units from the reprogramming data area or additional-programming data ar ea to the flash memory. the program address and 128-byte data are latched in the flash memory. the lower 8 bits of the start addr ess in the flash memory destination area must be h'00 or h'80. 5. the time during which the p bit is set to 1 is the programming time. table 7.6 shows the allowable programming times. 6. the watchdog timer (wdt) is set to prevent overprogramming due to program runaway, etc. an overflow cycle of approximately 6.6 ms is allowed. 7. for a dummy write to a verify address, write 1- byte data h'ff to an address whose lower 2 bits are b'00. verify data can be read in words or in longwords from the address to which a dummy write was performed.
section 7 rom rev. 6.00 mar. 24, 2006 page 105 of 412 rej09b0142-0600 8. the maximum number of repetitions of the pr ogram/program-verify sequence of the same bit is 1,000. start end of programming note: * the rts instruction must not be used during the following 1. and 2. periods. 1. a period between 128-byte data programming to flash memory and the p bit clearing 2. a period between dummy writing of h'ff to a verify address and verify data reading set swe bit in flmcr1 write pulse application subroutine wait 1 s apply write pulse * end sub set psu bit in flmcr1 wdt enable disable wdt wait 50 s set p bit in flmcr1 wait (wait time=programming time) clear p bit in flmcr1 wait 5 s clear psu bit in flmcr1 wait 5 s n= 1 m= 0 no no no yes yes yes yes wait 4 s wait 2 s wait 2 s apply write pulse set pv bit in flmcr1 set block start address as verify address h'ff dummy write to verify address read verify data verify data = write data? reprogram data computation additional-programming data computation clear pv bit in flmcr1 clear swe bit in flmcr1 m = 1 m= 0 ? increment address programming failure no clear swe bit in flmcr1 wait 100 s no yes n 6? no yes n 6 ? wait 100 s n 1000 ? n n + 1 write 128-byte data in ram reprogram data area consecutively to flash memory store 128-byte program data in program data area and reprogram data area apply write pulse sub-routine-call 128-byte data verification completed? successively write 128-byte data from additional- programming data area in ram to flash memory * figure 7.3 program/program-verify flowchart
section 7 rom rev. 6.00 mar. 24, 2006 page 106 of 412 rej09b0142-0600 table 7.4 reprogram data computation table program data verify data reprogram data comments 0 0 1 programming completed 0 1 0 reprogram bit 1 0 1 ? 1 1 1 remains in erased state table 7.5 additional-program data computation table reprogram data verify data additional-program data comments 0 0 0 additional-program bit 0 1 1 no additional programming 1 0 1 no additional programming 1 1 1 no additional programming table 7.6 programming time n (number of writes) programming time in additional programming comments 1 to 6 30 10 7 to 1,000 200 ? note: time shown in s.
section 7 rom rev. 6.00 mar. 24, 2006 page 107 of 412 rej09b0142-0600 7.4.2 erase/erase-verify when erasing flash memory, the erase/erase-veri fy flowchart shown in figure 7.4 should be followed. 1. prewriting (setting erase block data to all 0s) is not necessary. 2. erasing is performed in block units. make only a single-bit specification in the erase block register (ebr1). to erase multiple blocks, each block must be erased in turn. 3. the time during which the e bit is set to 1 is the flash memory erase time. 4. the watchdog timer (wdt) is set to prevent ov ererasing due to program runaway, etc. an overflow cycle of approximately 19.8 ms is allowed. 5. for a dummy write to a verify address, write 1-byte data h'ff to an address whose lower two bits are b'00. verify data can be read in lo ngwords from the address to which a dummy write was performed. 6. if the read data is not erased successfully, se t erase mode again, and repeat the erase/erase- verify sequence as before. the maximum numb er of repetitions of the erase/erase-verify sequence is 100. 7.4.3 interrupt handli ng when programming/erasing flash memory all interrupts, including the nmi interrupt, are disabled while flash memory is being programmed or erased, or while the boot program is executing, for the following three reasons: 1. interrupt during programming/erasing may cause a violation of the programming or erasing algorithm, with the result that normal operation cannot be assured. 2. if interrupt exception handling starts before the vector address is written or during programming/erasing, a correct vector cannot be fetched and the cpu malfunctions. 3. if an interrupt occurs during boot program execution, normal boot mode sequence cannot be carried out.
section 7 rom rev. 6.00 mar. 24, 2006 page 108 of 412 rej09b0142-0600 erase start set ebr1 enable wdt wait 1 s wait 100 s swe bit 1 n 1 esu bit 1 e bit 1 wait 10 ms e bit 0 wait 10 s esu bit 10 10 s disable wdt read verify data increment address verify data + all 1s ? last address of block ? all erase block erased ? set block start address as verify address h'ff dummy write to verify address wait 20 s wait 2 s ev bit 1 wait 100 s end of erasing note: * the rts instruction must not be used during a period between dummy writing of h'ff to a verify address and verify data reading. swe bit 0 wait 4 s ev bit 0 n 100 ? wait 100 s erase failure swe bit 0 wait 4 s ev bit 0 n n + 1 ye s no ye s ye s ye s no no no * figure 7.4 erase/erase-verify flowchart
section 7 rom rev. 6.00 mar. 24, 2006 page 109 of 412 rej09b0142-0600 7.5 program/erase protection there are three kinds of flash memory program/erase protection; hardware protection, software protection, and error protection. 7.5.1 hardware protection hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to reset, subactive mode, subsleep mode, or standby mode. flash memory control register 1 (flmcr1), flash memory control register 2 (flmcr2), and erase block register 1 (ebr1) ar e initialized. in a reset via the res pin, the reset state is not entered unless the res pin is held low until oscillation stab ilizes after powering on. in the case of a reset during operation, hold the res pin low for the res pulse width specified in the ac characteristic s section. 7.5.2 software protection software protection can be implemented against programming/erasing of all flash memory blocks by clearing the swe bit in flmcr1. when software protection is in effect, setting the p or e bit in flmcr1 does not cause a transition to prog ram mode or erase mode. by setting the erase block register 1 (ebr1), erase protection can be set for individual blocks. when ebr1 is set to h'00, erase protection is set for all blocks. 7.5.3 error protection in error protection, an error is detected when cpu runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the prog ram/erase operation is aborted. ab orting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. when the following errors are de tected during programming/eras ing of flash memory, the fler bit in flmcr2 is set to 1, and the error protection state is entered. ? ? ?
section 7 rom rev. 6.00 mar. 24, 2006 page 110 of 412 rej09b0142-0600 the flmcr1, flmcr2, and ebr1 settings are retained, however program mode or erase mode is aborted at the point at which the error occurr ed. program mode or erase mode cannot be re- entered by re-setting the p or e bit. however, pv and ev bit setting is enabled, and a transition can be made to verify mode. error protection can be cleared only by a power-on reset. 7.6 programmer mode in programmer mode, a prom programmer can be used to perform programming/erasing via a socket adapter, just as a discrete flash memo ry. use a prom programmer that supports the mcu device type with the on-chip 64-kbyte flash memory (fztat64v5). 7.7 power-down states for flash memory in user mode, the flash memory will operate in either of the following states: ? ? ?
section 7 rom rev. 6.00 mar. 24, 2006 page 111 of 412 rej09b0142-0600 table 7.7 flash memory operating states flash memory operating state lsi operating state pdwnd = 0 (initial value) pdwnd = 1 active mode normal operating mode normal operating mode subactive mode power-down mode normal operating mode sleep mode normal operating mode normal operating mode subsleep mode standby mode standby mode standby mode standby mode standby mode
section 7 rom rev. 6.00 mar. 24, 2006 page 112 of 412 rej09b0142-0600
section 8 ram rev. 6.00 mar. 24, 2006 page 113 of 412 rej09b0142-0600 section 8 ram this lsi has an on-chip high-speed static ram. the ram is connected to the cpu by a 16-bit data bus, enabling two-state access by the cpu to both byte data and word data. product classification ram size ram address flash memory version h8/3664n 2 kbytes h'f780 to h'ff7f * (f-ztat tm version) h8/3664f 2 kbytes h'f780 to h'ff7f * mask rom version h8/3664 1 kbyte h'fb80 to h'ff7f h8/3663 1 kbyte h'fb80 to h'ff7f h8/3662 512 bytes h'fd80 to h'ff7f h8/3661 512 bytes h'fd80 to h'ff7f h8/3660 512 bytes h'fd80 to h'ff7f note: * area h'f780 to h'fb7f must not be accessed.
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section 9 i/o ports rev. 6.00 mar. 24, 2006 page 115 of 412 rej09b0142-0600 section 9 i/o ports the group of this lsi has twenty-nine general i/o ports (twenty-seven ports for h8/3664n) and eight general input-only ports. port 8 is a large current port, which can drive 20 ma (@v ol = 1.5 v) when a low level signal is output. any of these ports can become an input port immediately after a reset. they can also be used as i/o pins of the on-chip peripheral modules or external interrupt input pins, and these functions can be switched depending on the register settings. the registers for selecting these functions can be divided into two types: those included in i/o ports and those included in each on-chip peripheral modu le. general i/o ports are comprised of the port control register for controlling inputs/outputs and the port data register for storing output data and can select inputs/outputs in bit units. for functions in each port, see appendix b.1, i/o port block. for the execution of bit manipulation instructions to the port control register and port data register, see section 2.8.3, bit manipulation instruction. 9.1 port 1 port 1 is a general i/o port also functioning as irq interrupt input pins, a timer a output pin, and a timer v input pin. figure 9.1 shows its pin configuration. p17/ irq3 /trgv p16/ irq2 p15/ irq1 p14/ irq0 p12 p11 p10/tmow port 1 figure 9.1 port 1 pin configuration port 1 has the following registers. ? port mode register 1 (pmr1) ? port control register 1 (pcr1) ? port data register 1 (pdr1) ? port pull-up control register 1 (pucr1)
section 9 i/o ports rev. 6.00 mar. 24, 2006 page 116 of 412 rej09b0142-0600 9.1.1 port mode register 1 (pmr1) pmr1 switches the functions of pins in port 1 and port 2. bit bit name initial value r/w description 7 irq3 0 r/w p17/ irq3 /trgv pin function switch this bit selects whether pin p17/ irq3 /trgv is used as p17 or as irq3 /trgv. 0: general i/o port 1: irq3 /trgv input pin 6 irq2 0 r/w p16/ irq2 pin function switch this bit selects whether pin p16/ irq2 is used as p16 or as irq2 . 0: general i/o port 1: irq2 input pin 5 irq1 0 r/w p15/ irq1 pin function switch this bit selects whether pin p15/ irq1 is used as p15 or as irq1 . 0: general i/o port 1: irq1 input pin 4 irq0 0 r/w p14/ irq0 pin function switch this bit selects whether pin p14/ irq0 is used as p14 or as irq0 . 0: general i/o port 1: irq0 input pin 3 2 ? ? 1 1 ? ? reserved these bits are always read as 1. 1 txd 0 r/w p22/txd pin function switch this bit selects whether pin p22/txd is used as p22 or as txd. 0: general i/o port 1: txd output pin
section 9 i/o ports rev. 6.00 mar. 24, 2006 page 117 of 412 rej09b0142-0600 bit bit name initial value r/w description 0 tmow 0 r/w p10/tmow pin function switch this bit selects whether pin p10/tmow is used as p10 or as tmow. 0: general i/o port 1: tmow output pin 9.1.2 port control register 1 (pcr1) pcr1 selects inputs/outputs in bit units for pins to be used as general i/o ports of port 1. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pcr17 pcr16 pcr15 pcr14 ? pcr12 pcr11 pcr10 0 0 0 0 ? 0 0 0 w w w w ? w w w when the corresponding pin is designated in pmr1 as a general i/o pin, setting a pcr1 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. bit 3 is a reserved bit.
section 9 i/o ports rev. 6.00 mar. 24, 2006 page 118 of 412 rej09b0142-0600 9.1.3 port data register 1 (pdr1) pdr1 is a general i/o port data register of port 1. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 p17 p16 p15 p14 ? p12 p11 p10 0 0 0 0 1 0 0 0 r/w r/w r/w r/w ? r/w r/w r/w pdr1 stores output data for port 1 pins. if pdr1 is read while pcr1 bi ts are set to 1, the value stored in pdr1 are read. if pdr1 is read while pcr1 bits are cleared to 0, the pi n states are read regardless of the value stored in pdr1. bit 3 is a reserved bit. this bit is always read as 1. 9.1.4 port pull-up control register 1 (pucr1) pucr1 controls the pull-up mos in bit units of the pins set as the input ports. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pucr17 pucr16 pucr15 pucr14 ? pucr12 pucr11 pucr10 0 0 0 0 1 0 0 0 r/w r/w r/w r/w ? r/w r/w r/w only bits for which pcr1 is cleared are valid. the pull- up mos of p17 to p14 and p12 to p10 pins enter the on-state when these bits are set to 1, while they enter the off-state when these bi ts are cleared to 0. bit 3 is a reserved bit. this bit is always read as 1.
section 9 i/o ports rev. 6.00 mar. 24, 2006 page 119 of 412 rej09b0142-0600 9.1.5 pin functions the correspondence between the register specification and the port functions is shown below. ? p17/ irq3 /trgv pin register pmr1 pcr1 bit name irq3 pcr17 pin function setting value 0 0 p17 input pin 1 p17 output pin 1 x irq3 input/trgv input pin [legend] x: don't care. ? p16/ irq2 pin register pmr1 pcr1 bit name irq2 pcr16 pin function setting value 0 0 p16 input pin 1 p16 output pin 1 x irq2 input pin [legend] x: don't care. ? p15/ irq1 pin register pmr1 pcr1 bit name irq1 pcr15 pin function setting value 0 0 p15 input pin 1 p15 output pin 1 x irq1 input pin [legend] x: don't care.
section 9 i/o ports rev. 6.00 mar. 24, 2006 page 120 of 412 rej09b0142-0600 ? p14/ irq0 pin register pmr1 pcr1 bit name irq0 pcr14 pin function setting value 0 0 p14 input pin 1 p14 output pin 1 x irq0 input pin [legend] x: don't care. ? p12 pin register pcr1 bit name pcr12 pin function 0 p12 input pin setting value 1 p12 output pin ? p11 pin register pcr1 bit name pcr11 pin function 0 p11 input pin setting value 1 p11 output pin ? p10/tmow pin register pmr1 pcr1 bit name tmow pcr10 pin function setting value 0 0 p10 input pin 1 p10 output pin 1 x tmow output pin [legend] x: don't care.
section 9 i/o ports rev. 6.00 mar. 24, 2006 page 121 of 412 rej09b0142-0600 9.2 port 2 port 2 is a general i/o port also functioning as a sci3 i/o pin. each pin of the port 2 is shown in figure 9.2. the register settings of pmr1 and sci3 have priority for functions of the pins for both uses. p22/txd p21/rxd p20/sck3 port 2 figure 9.2 port 2 pin configuration port 2 has the following registers. ? port control register 2 (pcr2) ? port data register 2 (pdr2) 9.2.1 port control register 2 (pcr2) pcr2 selects inputs/outputs in bit units for pins to be used as general i/o ports of port 2. bit bit name initial value r/w description 7 6 5 4 3 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? reserved 2 1 0 pcr22 pcr21 pcr20 0 0 0 w w w when each of the port 2 pins p22 to p20 functions as an general i/o port, setting a pcr2 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port.
section 9 i/o ports rev. 6.00 mar. 24, 2006 page 122 of 412 rej09b0142-0600 9.2.2 port data register 2 (pdr2) pdr2 is a general i/o port data register of port 2. bit bit name initial value r/w description 7 6 5 4 3 ? ? ? ? ? 1 1 1 1 1 ? ? ? ? ? reserved these bits are always read as 1. 2 1 0 p22 p21 p20 0 0 0 r/w r/w r/w pdr2 stores output data for port 2 pins. pdr2 is read while pcr2 bits are set to 1, the value stored in pdr2 is read. if pdr2 is read while pcr2 bits are cleared to 0, the pin st ates are read regardless of the value stored in pdr2. 9.2.3 pin functions the correspondence between the register specification and the port functions is shown below. ? p22/txd pin register pmr1 pcr2 bit name txd pcr22 pin function setting value 0 0 p22 input pin 1 p22 output pin 1 x txd output pin [legend] x: don't care.
section 9 i/o ports rev. 6.00 mar. 24, 2006 page 123 of 412 rej09b0142-0600 ? p21/rxd pin register scr3 pcr2 bit name re pcr21 pin function setting value 0 0 p21 input pin 1 p21 output pin 1 x rxd input pin [legend] x: don't care. ? p20/sck3 pin register scr3 smr pcr2 bit name cke1 cke0 com pcr20 pin function setting value 0 0 0 0 p20 input pin 1 p20 output pin 0 0 1 x sck3 output pin 0 1 x x sck3 output pin 1 x x x sck3 input pin [legend] x: don't care.
section 9 i/o ports rev. 6.00 mar. 24, 2006 page 124 of 412 rej09b0142-0600 9.3 port 5 port 5 is a general i/o port also functioning as an i 2 c bus interface i/o pin, an a/d trigger input pin, wakeup interrupt input pin. each pin of the port 5 is shown in figure 9.3. the register setting of the i 2 c bus interface register has priority for functions of the pins p57/scl and p56/sda. since the output buffer for pins p56 and p57 has the nmos push-pull structure, it differs from an output buffer with the cmos structure in the high-level output characteristics (see section 20, electrical characteristics). the h8/3664n does not have p57 and p56. p57/scl p56/sda p55/ wkp5 / adtrg p54/ wkp4 p53/ wkp3 p52/ wkp2 p51/ wkp1 p50/ wkp0 port 5 scl sda p55/ wkp5 / adtr g p54/ wkp4 p53/ wkp3 p52/ wkp2 p51/ wkp1 p50/ wkp0 port 5 h8/3664 h8/3664n figure 9.3 port 5 pin configuration port 5 has the following registers. ? port mode register 5 (pmr5) ? port control register 5 (pcr5) ? port data register 5 (pdr5) ? port pull-up control register 5 (pucr5)
section 9 i/o ports rev. 6.00 mar. 24, 2006 page 125 of 412 rej09b0142-0600 9.3.1 port mode register 5 (pmr5) pmr5 switches the functions of pins in port 5. bit bit name initial value r/w description 7 6 ? ? 0 0 ? ? reserved these bits are always read as 0. 5 wkp5 0 r/w p55/ wkp5 / adtrg pin function switch selects whether pin p55/ wkp5 / adtrg is used as p55 or as wkp5 / adtrg input. 0: general i/o port 1: wkp5 / adtrg input pin 4 wkp4 0 r/w p54/ wkp4 pin function switch selects whether pin p54/ wkp4 is used as p54 or as wkp4 . 0: general i/o port 1: wkp4 input pin 3 wkp3 0 r/w p53/ wkp3 pin function switch selects whether pin p53/ wkp3 is used as p53 or as wkp3 . 0: general i/o port 1: wkp3 input pin 2 wkp2 0 r/w p52/ wkp2 pin function switch selects whether pin p52/ wkp2 is used as p52 or as wkp2 . 0: general i/o port 1: wkp2 input pin 1 wkp1 0 r/w p51/ wkp1 pin function switch selects whether pin p51/ wkp1 is used as p51 or as wkp1 . 0: general i/o port 1: wkp1 input pin
section 9 i/o ports rev. 6.00 mar. 24, 2006 page 126 of 412 rej09b0142-0600 bit bit name initial value r/w description 0 wkp0 0 r/w p50/ wkp0 pin function switch selects whether pin p50/ wkp0 is used as p50 or as wkp0 . 0: general i/o port 1: wkp0 input pin 9.3.2 port control register 5 (pcr5) pcr5 selects inputs/outputs in bit units for pins to be used as general i/o ports of port 5. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pcr57 pcr56 pcr55 pcr54 pcr53 pcr52 pcr51 pcr50 0 0 0 0 0 0 0 0 w w w w w w w w when each of the port 5 pins p57 to p50 functions as an general i/o port, setting a pcr5 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. note: do not set pcr57 and pcr56 to 1 for h8/3664n.
section 9 i/o ports rev. 6.00 mar. 24, 2006 page 127 of 412 rej09b0142-0600 9.3.3 port data register 5 (pdr5) pdr5 is a general i/o port data register of port 5. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 p57 p56 p55 p54 p53 p52 p51 p50 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w stores output data for port 5 pins. if pdr5 is read while pcr5 bi ts are set to 1, the value stored in pdr5 are read. if pdr5 is read while pcr5 bits are cleared to 0, the pi n states are read regardless of the value stored in pdr5. note: do not set p57 and p56 to 1 for h8/3664n. 9.3.4 port pull-up control register 5 (pucr5) pucr5 controls the pull-up mos in bit units of the pins set as the input ports. bit bit name initial value r/w description 7 6 ? ? 0 0 ? ? reserved these bits are always read as 0. 5 4 3 2 1 0 pucr55 pucr54 pucr53 pucr52 pucr51 pucr50 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w only bits for which pcr5 is cleared are valid. the pull- up mos of the corresponding pins enter the on-state when these bits are set to 1, while they enter the off- state when these bits are cleared to 0.
section 9 i/o ports rev. 6.00 mar. 24, 2006 page 128 of 412 rej09b0142-0600 9.3.5 pin functions the correspondence between the register specification and the port functions is shown below. ? p57/scl pin register iccr pcr5 bit name ice pcr57 pin function setting value 0 0 p57 input pin 1 p57 output pin 1 x scl i/o pin [legend] x: don't care. scl performs the nmos open-drain output, that enables a direct bus drive. ? p56/sda pin register iccr pcr5 bit name ice pcr56 pin function setting value 0 0 p56 input pin 1 p56 output pin 1 x sda i/o pin [legend] x: don't care. sda performs the nmos open-drain output, that enables a direct bus drive. ? p55/ wkp5 / adtrg pin register pmr5 pcr5 bit name wkp5 pcr55 pin function setting value 0 0 p55 input pin 1 p55 output pin 1 x wkp5 / adtrg input pin [legend] x: don't care.
section 9 i/o ports rev. 6.00 mar. 24, 2006 page 129 of 412 rej09b0142-0600 ? p54/ wkp4 pin register pmr5 pcr5 bit name wkp4 pcr54 pin function setting value 0 0 p54 input pin 1 p54 output pin 1 x wkp4 input pin [legend] x: don't care. ? p53/ wkp3 pin register pmr5 pcr5 bit name wkp3 pcr53 pin function setting value 0 0 p53 input pin 1 p53 output pin 1 x wkp3 input pin [legend] x: don't care. ? p52/ wkp2 pin register pmr5 pcr5 bit name wkp2 pcr52 pin function setting value 0 0 p52 input pin 1 p52 output pin 1 x wkp2 input pin [legend] x: don't care.
section 9 i/o ports rev. 6.00 mar. 24, 2006 page 130 of 412 rej09b0142-0600 ? p51/ wkp1 pin register pmr5 pcr5 bit name wkp1 pcr51 pin function setting value 0 0 p51 input pin 1 p51 output pin 1 x wkp1 input pin [legend] x: don't care. ? p50/ wkp0 pin register pmr5 pcr5 bit name wkp0 pcr50 pin function setting value 0 0 p50 input pin 1 p50 output pin 1 x wkp0 input pin [legend] x: don't care. 9.4 port 7 port 7 is a general i/o port also functioning as a timer v i/o pin. each pin of the port 7 is shown in figure 9.4. the register setting of tcsrv in timer v has priority for functions of pin p76/tmov. the pins, p75/tmciv and p74/tmriv, are also functioning as timer v input ports that are connected to the timer v regardle ss of the register setting of port 7. p76/tmov p75/tmciv p74/tmriv port 7 figure 9.4 port 7 pin configuration
section 9 i/o ports rev. 6.00 mar. 24, 2006 page 131 of 412 rej09b0142-0600 port 7 has the following registers. ? port control register 7 (pcr7) ? port data register 7 (pdr7) 9.4.1 port control register 7 (pcr7) pcr7 selects inputs/outputs in bit units for pins to be used as general i/o ports of port 7. bit bit name initial value r/w description 7 ? ? ? reserved 6 5 4 pcr76 pcr75 pcr74 0 0 0 w w w setting a pcr7 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. note that the tcsrv setting of the timer v has priority for deciding in put/output direction of the p76/tmov pin. 3 2 1 0 ? ? ? ? ? ? ? ? ? ? ? ? reserved 9.4.2 port data register 7 (pdr7) pdr7 is a general i/o port data register of port 7. bit bit name initial value r/w description 7 ? 1 ? reserved this bit is always read as 1. 6 5 4 p76 p75 p74 0 0 0 r/w r/w r/w pdr7 stores output data for port 7 pins. pdr7 is read while pcr7 bits are set to 1, the value stored in pdr7 is read. if pdr7 is read while pcr7 bits are cleared to 0, the pin st ates are read regardless of the value stored in pdr7. 3 2 1 0 ? ? ? ? 1 1 1 1 ? ? ? ? reserved these bits are always read as 1.
section 9 i/o ports rev. 6.00 mar. 24, 2006 page 132 of 412 rej09b0142-0600 9.4.3 pin functions the correspondence between the register specification and the port functions is shown below. ? p76/tmov pin register tcsrv pcr7 bit name os3 to os0 pcr76 pin function setting value 0000 0 p76 input pin 1 p76 output pin other than the above values x tmov output pin [legend] x: don't care. ? p75/tmciv pin register pcr7 bit name pcr75 pin function setting value 0 p75 input/tmciv input pin 1 p75 output/tmciv input pin ? p74/tmriv pin register pcr7 bit name pcr74 pin function setting value 0 p74 input/tmriv input pin 1 p74 output/tmriv input pin
section 9 i/o ports rev. 6.00 mar. 24, 2006 page 133 of 412 rej09b0142-0600 9.5 port 8 port 8 is a general i/o port also functioning as a timer w i/o pin. each pin of the port 8 is shown in figure 9.5. the register setting of the timer w has priority for functions of the pins p84/ftiod, p83/ftioc, p82/ftiob, and p81/ftioa. p80/ftci also functions as a timer w input port that is connected to the timer w regardless of the register setting of port 8. p87 p86 p85 p84/ftiod p83/ftioc p82/ftiob p81/ftioa p80/ftci port 8 figure 9.5 port 8 pin configuration port 8 has the following registers. ? port control register 8 (pcr8) ? port data register 8 (pdr8)
section 9 i/o ports rev. 6.00 mar. 24, 2006 page 134 of 412 rej09b0142-0600 9.5.1 port control register 8 (pcr8) pcr8 selects inputs/outputs in bit units for pins to be used as general i/o ports of port 8. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pcr87 pcr86 pcr85 pcr84 pcr83 pcr82 pcr81 pcr80 0 0 0 0 0 0 0 0 w w w w w w w w when each of the port 8 pins p87 to p80 functions as an general i/o port, setting a pcr8 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. 9.5.2 port data register 8 (pdr8) pdr8 is a general i/o port data register of port 8. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 p87 p86 p85 p84 p83 p82 p81 p80 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w pdr8 stores output data for port 8 pins. pdr8 is read while pcr8 bits are set to 1, the value stored in pdr8 is read. if pdr8 is read while pcr8 bits are cleared to 0, the pin states are read regardless of the value stored in pdr8.
section 9 i/o ports rev. 6.00 mar. 24, 2006 page 135 of 412 rej09b0142-0600 9.5.3 pin functions the correspondence between the register specification and the port functions is shown below. ? p87 pin register pcr8 bit name pcr87 pin function setting value 0 p87 input pin 1 p87 output pin ? p86 pin register pcr8 bit name pcr86 pin function setting value 0 p86 input pin 1 p86 output pin ? p85 pin register pcr8 bit name pcr85 pin function setting value 0 p85 input pin 1 p85 output pin
section 9 i/o ports rev. 6.00 mar. 24, 2006 page 136 of 412 rej09b0142-0600 ? p84/ftiod pin register tmrw tior1 pcr8 bit name pwmd iod2 iod1 iod0 pcr84 pin function setting value 0 0 0 0 0 p84 input/ftiod input pin 1 p84 output/ftiod input pin 0 0 1 x ftiod output pin 0 1 x x ftiod output pin 1 x x 0 p84 input/ftiod input pin 1 p84 output/ftiod input pin 1 x x x x pwm output pin [legend] x: don't care. ? p83/ftioc pin register tmrw tior1 pcr8 bit name pwmc ioc2 ioc1 ioc0 pcr83 pin function setting value 0 0 0 0 0 p83 input/ftioc input pin 1 p83 output/ftioc input pin 0 0 1 x ftioc output pin 0 1 x x ftioc output pin 1 x x 0 p83 input/ftioc input pin 1 p83 output/ftioc input pin 1 x x x x pwm output pin [legend] x: don't care.
section 9 i/o ports rev. 6.00 mar. 24, 2006 page 137 of 412 rej09b0142-0600 ? p82/ftiob pin register tmrw tior0 pcr8 bit name pwmb iob2 iob1 iob0 pcr82 pin function setting value 0 0 0 0 0 p82 input/ftiob input pin 1 p82 output/ftiob input pin 0 0 1 x ftiob output pin 0 1 x x ftiob output pin 1 x x 0 p82 input/ftiob input pin 1 p82 output/ftiob input pin 1 x x x x pwm output pin [legend] x: don't care. ? p81/ftioa pin register tior0 pcr8 bit name ioa2 ioa1 ioa0 pcr81 pin function setting value 0 0 0 0 p81 input/ftioa input pin 0 1 p81 output/ftioa input pin 0 0 1 x ftioa output pin 0 1 x x ftioa output pin 1 x x 0 p81 input/ftioa input pin 1 p81 output/ftioa input pin [legend] x: don't care. ? p80/ftci pin register pcr8 bit name pcr80 pin function setting value 0 p80 input/ftci input pin 1 p80 output/ftci input pin
section 9 i/o ports rev. 6.00 mar. 24, 2006 page 138 of 412 rej09b0142-0600 9.6 port b port b is an input port also functioning as an a/d converter analog input pin. each pin of the port b is shown in figure 9.6. pb7/an7 pb6/an6 pb5/an5 pb4/an4 pb3/an3 pb2/an2 pb1/an1 pb0/an0 port b figure 9.6 port b pin configuration port b has the following register. ? port data register b (pdrb) 9.6.1 port data register b (pdrb) pdrb is a general input-only port data register of port b. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 ? ? ? ? ? ? ? ? r r r r r r r r the input value of each pin is read by reading this register. however, if a port b pin is designated as an analog input channel by adcsr in a/d converter, 0 is read.
section 10 timer a rev. 6.00 mar. 24, 2006 page 139 of 412 rej09b0142-0600 section 10 timer a timer a is an 8-bit timer with interval timing an d real-time clock time-base functions. the clock time-base function is available when a 32.768kh z crystal oscillator is connected. figure 10.1 shows a block diagram of timer a. 10.1 features ? ? ? interval timer: ? clock time base: ?
section 10 timer a rev. 6.00 mar. 24, 2006 page 140 of 412 rej09b0142-0600 w tmow w /32 w /16 w /8 w /4 w /32 w /16 w /8 w /4 /8192, /4096, /2048, /512, /256, /128, /32, /8 w /128 w /4 1/4 psw pss tma tca irrta 8 * 64 * 128 * 256 * [legend] tma: timer mode register a tca: timer counter a irrta: timer a overflow interrupt request flag psw: prescaler w pss: prescaler s note: * can be selected only when the prescaler w output (? w /128) is used as the tca input clock. internal data bus figure 10.1 block diagram of timer a 10.2 input/output pins table 10.1 shows the timer a input/output pin. table 10.1 pin configuration name abbreviation i/o function clock output tmow output out put of waveform generated by timer a output circuit
section 10 timer a rev. 6.00 mar. 24, 2006 page 141 of 412 rej09b0142-0600 10.3 register descriptions timer a has the following registers. ? ? 10.3.1 timer mode register a (tma) tma selects the operating mode, the divided clock output, and the input clock. bit bit name initial value r/w description 7 6 5 tma7 tma6 tma5 0 0 0 r/w r/w r/w clock output select 7 to 5 these bits select the clo ck output at the tmow pin. 000: /32 001: /16 010: /8 011: /4 100: w /32 101: w /16 110: w /8 111: w /4 for details on clock outputs, see section 10.4.3, clock output. 4 ? 1 ? reserved this bit is always read as 1. 3 tma3 0 r/w internal clock select 3 this bit selects the operating mode of the timer a. 0: functions as an interval timer to count the outputs of prescaler s. 1: functions as a clock-time base to count the outputs of prescaler w.
section 10 timer a rev. 6.00 mar. 24, 2006 page 142 of 412 rej09b0142-0600 bit bit name initial value r/w description 2 1 0 tma2 tma1 tma0 0 0 0 r/w r/w r/w internal clock select 2 to 0 these bits select the clock input to tca when tma3 = 0. 000: /8192 001: /4096 010: /2048 011: /512 100: /256 101: /128 110: /32 111: /8 these bits select the overflow period when tma3 = 1 (when a 32.768 khz crystal oscillator with is used as w). 000: 1s 001: 0.5 s 010: 0.25 s 011: 0.03125 s 1xx: both psw and tca are reset [legend] x: don't care. 10.3.2 timer counter a (tca) tca is an 8-bit readable up-counter, which is incremented by internal clock input. the clock source for input to this counter is selected by bits tma3 to tma0 in tma. tca values can be read by the cpu in active mode, but cannot be r ead in subactive mode. wh en tca overflows, the irrta bit in interrupt request register 1 (irr1) is set to 1. tca is cleared by setting bits tma3 and tma2 in tma to b?11. tca is initialized to h'00.
section 10 timer a rev. 6.00 mar. 24, 2006 page 143 of 412 rej09b0142-0600 10.4 operation 10.4.1 interval timer operation when bit tma3 in tma is cleared to 0, timer a functions as an 8-bit interval timer. upon reset, tca is cleared to h'00 and bit tma3 is cleared to 0, so up-counting of timer a resume immediately as an interval timer. the clock input to timer a is selected by bits tma2 to tma0 in tma; any of eight in ternal clock signals output by prescaler s can be selected. after the count value in tca reaches h'ff, th e next clock signal input causes timer a to overflow, setting bit irrta to 1 in interrupt flag register 1 (irr1). if ienta = 1 in interrupt enable register 1 (ienr1), a cpu interrupt is re quested. at overflow, tca returns to h'00 and starts counting up again. in this mode timer a fu nctions as an interval timer that generates an overflow output at intervals of 256 input clock pulses. 10.4.2 clock time base operation when bit tma3 in tma is set to 1, timer a functions as a clock-timer base by counting clock signals output by prescaler w. when a clock si gnal is input after the tca counter value has become h'ff, timer a overflows and irrta in irr1 is set to 1. at that time, an interrupt request is generated to the cpu if ienta in the interrupt enable register 1 (ienr1) is 1. the overflow period of timer a is set by bits tma1 and tma0 in tma. a choice of four periods is available. in clock time base operation (tma3 = 1), setting bit tma2 to 1 clears both tca and prescaler w to h'00. 10.4.3 clock output setting bit tmow in port mode register 1 (pmr1) to 1 causes a clock signal to be output at pin tmow. eight different clock output signals can be selected by means of bits tma7 to tma5 in tma. the system clock divided by 32, 16, 8, or 4 can be output in active mode and sleep mode. a 32.768 khz signal divided by 32, 16, 8, or 4 can be output in active mode, sleep mode, and subactive mode.
section 10 timer a rev. 6.00 mar. 24, 2006 page 144 of 412 rej09b0142-0600 10.5 usage note when the clock time base function is selected as th e internal clock of tca in active mode or sleep mode, the internal clock is not synchronous with the system clock, so it is synchronized by a synchronizing circuit. this may result in a maximum error of 1/
section 11 timer v rev. 6.00 mar. 24, 2006 page 145 of 412 rej09b0142-0600 section 11 timer v timer v is an 8-bit timer based on an 8-bit counter. timer v counts external events. compare- match signals with two registers can also be used to reset the counter, request an interrupt, or output a pulse signal with an arbitrary duty cycle. counting can be initiated by a trigger input at the trgv pin, enabling pulse output control to be synchronized to the trigger, with an arbitrary delay from the trigger input. figure 11.1 shows a block diagram of timer v. 11.1 features ? ? ? ? ?
section 11 timer v rev. 6.00 mar. 24, 2006 page 146 of 412 rej09b0142-0600 trgv tmciv tmriv tmov trigger control clock select clear control output control pss tcrv1 tcorb comparator tcntv comparator tcora tcrv0 interrupt request control tcsrv cmia cmib ovi internal data bus [legend] tcora: time constant register a tcorb: time constant register b tcntv: timer counter v tcsrv: timer control/status register v tcrv0: timer control register v0 tcrv1: timer control register v1 pss: prescaler s cmia: compare-match interrupt a cmib: compare-match interrupt b ovi: overflow interupt figure 11.1 block diagram of timer v
section 11 timer v rev. 6.00 mar. 24, 2006 page 147 of 412 rej09b0142-0600 11.2 input/output pins table 11.1 shows the timer v pin configuration. table 11.1 pin configuration name abbreviation i/o function timer v output tmov output timer v waveform output timer v clock input tmciv input clock input to tcntv timer v reset input tmriv input external input to reset tcntv trigger input trgv input trigger input to initiate counting 11.3 register descriptions time v has the following registers. ? ? ? ? ? ? 11.3.1 timer counter v (tcntv) tcntv is an 8-bit up-counter. the clock source is selected by bits cks2 to cks0 in timer control register v0 (tcrv0). the tcntv value can be read and written by the cpu at any time. tcntv can be cleared by an external reset in put signal, or by compare match a or b. the clearing signal is selected by bits cclr1 and cclr0 in tcrv0. when tcntv overflows, ovf is set to 1 in timer control/status register v (tcsrv). tcntv is initialized to h'00.
section 11 timer v rev. 6.00 mar. 24, 2006 page 148 of 412 rej09b0142-0600 11.3.2 time constant registers a and b (tcora, tcorb) tcora and tcorb have the same function. tcora and tcorb are 8-bit read/write registers. tcora and tcntv are compared at all times. when the tcora and tcntv contents match, cmfa is set to 1 in tcsrv. if cmiea is also se t to 1 in tcrv0, a cpu interrupt is requested. note that they must not be compared duri ng the t3 state of a tcora write cycle. timer output from the tmov pin can be controlled by the identifying signal (compare match a) and the settings of bits os3 to os0 in tcsrv. tcora and tcorb are initialized to h'ff. 11.3.3 timer control register v0 (tcrv0) tcrv0 selects the input clock signals of tcntv, specifies the clearing conditions of tcntv, and controls each interrupt request. bit bit name initial value r/w description 7 cmieb 0 r/w compare match interrupt enable b when this bit is set to 1, interrupt request from the cmfb bit in tcsrv is enabled. 6 cmiea 0 r/w compare match interrupt enable a when this bit is set to 1, interrupt request from the cmfa bit in tcsrv is enabled. 5 ovie 0 r/w timer overflow interrupt enable when this bit is set to 1, interrupt request from the ovf bit in tcsrv is enabled.
section 11 timer v rev. 6.00 mar. 24, 2006 page 149 of 412 rej09b0142-0600 bit bit name initial value r/w description 4 3 cclr1 cclr0 0 0 r/w r/w counter clear 1 and 0 these bits specify the clear ing conditions of tcntv. 00: clearing is disabled 01: cleared by compare match a 10: cleared by compare match b 11: cleared on the rising edge of the tmriv pin. the operation of tcntv after clearing depends on trge in tcrv1. 2 1 0 cks2 cks1 cks0 0 0 0 r/w r/w r/w clock select 2 to 0 these bits select clock signals to input to tcntv and the counting condition in combination with icks0 in tcrv1. refer to table 11.2. table 11.2 clock signals to input to tcntv and counting conditions tcrv0 tcrv1 bit 2 bit 1 bit 0 bit 0 cks2 cks1 cks0 icks0 description 0 0 0 ? clock input prohibited 1 0 internal clock: counts on /4, falling edge 1 internal clock: counts on /8, falling edge 1 0 0 internal clock: counts on /16, falling edge 1 internal clock: counts on /32, falling edge 1 0 internal clock: counts on /64, falling edge 1 internal clock: counts on /128, falling edge 1 0 0 ? clock input prohibited 1 ? external clock: counts on rising edge 1 0 ? external clock: counts on falling edge 1 ? external clock: counts on rising and falling edge
section 11 timer v rev. 6.00 mar. 24, 2006 page 150 of 412 rej09b0142-0600 11.3.4 timer control/st atus register v (tcsrv) tcsrv indicates the status flag and controls outputs by using a compare match. bit bit name initial value r/w description 7 cmfb 0 r/w compare match flag b setting condition: when the tcntv value matches the tcorb value clearing condition: after reading cmfb = 1, cleared by writing 0 to cmfb 6 cmfa 0 r/w compare match flag a setting condition: when the tcntv value matches the tcora value clearing condition: after reading cmfa = 1, cleared by writing 0 to cmfa 5 ovf 0 r/w timer overflow flag setting condition: when tcntv overflows from h'ff to h'00 clearing condition: after reading ovf = 1, cleared by writing 0 to ovf 4 ? 1 ? reserved this bit is always read as 1. 3 2 os3 os2 0 0 r/w r/w output select 3 and 2 these bits select an output method for the tmov pin by the compare match of tcorb and tcntv. 00: no change 01: 0 output 10: 1 output 11: output toggles
section 11 timer v rev. 6.00 mar. 24, 2006 page 151 of 412 rej09b0142-0600 bit bit name initial value r/w description 1 0 os1 os0 0 0 r/w r/w output select 1 and 0 these bits select an output method for the tmov pin by the compare match of tcora and tcntv. 00: no change 01: 0 output 10: 1 output 11: output toggles os3 and os2 select the output level for compare match b. os1 and os0 select the output level for compare match a. the two output levels can be controlled independently. after a reset, the timer output is 0 until the first compare match. 11.3.5 timer control register v1 (tcrv1) tcrv1 selects the edge at the trgv pin, enab les trgv input, and selects the clock input to tcntv. bit bit name initial value r/w description 7 to 5 ? all 1 ? reserved these bits are always read as 1. 4 3 tveg1 tveg0 0 0 r/w r/w trgv input edge select these bits select the trgv input edge. 00: trgv trigger input is prohibited 01: rising edge is selected 10: falling edge is selected 11: rising and falling edges are both selected 2 trge 0 r/w tcntv starts count ing up by the input of the edge which is selected by tveg1 and tveg0. 0: disables starting counting- up tcntv by the input of the trgv pin and halting counting-up tcntv when tcntv is cleared by a compare match. 1: enables starting counting- up tcntv by the input of the trgv pin and halting counting-up tcntv when tcntv is cleared by a compare match.
section 11 timer v rev. 6.00 mar. 24, 2006 page 152 of 412 rej09b0142-0600 bit bit name initial value r/w description 1 ? 1 ? reserved this bit is always read as 1. 0 icks0 0 r/w internal clock select 0 this bit selects clock sign als to input to tcntv in combination with cks2 to cks0 in tcrv0. refer to table 11.2. 11.4 operation 11.4.1 timer v operation 1. according to table 11.2, six internal/external clock signals output by prescaler s can be selected as the timer v operating clock signals . when the operating cl ock signal is selected, tcntv starts counting-up. figure 11.2 shows the count timing with an internal clock signal selected, and figure 11.3 shows the count timing with both edges of an external clock signal selected. 2. when tcntv overflows (changes from h'ff to h'00), the overflow flag (ovf) in tcrv0 will be set. the timing at this time is shown in fi gure 11.4. an interrupt request is sent to the cpu when ovie in tcrv0 is 1. 3. tcntv is constantly compared with tcora and tcorb. compare match flag a or b (cmfa or cmfb) is set to 1 when tcntv ma tches tcora or tcorb, respectively. the compare-match signal is generated in the last state in which the values match. figure 11.5 shows the timing. an interrupt request is generated for the cpu when cmiea or cmieb in tcrv0 is 1. 4. when a compare match a or b is generated, the tmov responds with the output value selected by bits os3 to os0 in tcsrv. figure 11.6 shows the timing when the output is toggled by compare match a. 5. when cclr1 or cclr0 in tcrv0 is 01 or 10, tcntv can be cleared by the corresponding compare match. figure 11.7 shows the timing. 6. when cclr1 or cclr0 in tcrv0 is 11, tcnt v can be cleared by the rising edge of the input of tmriv pin. a tmriv input pulse-width of at least 1.5 system clocks is necessary. figure 11.8 shows the timing. 7. when a counter-clearing source is generated with trge in tcrv1 set to 1, the counting-up is halted as soon as tcntv is cleared. tcntv resu mes counting-up when the edge selected by tveg1 or tveg0 in tcrv1 is input from the tgrv pin.
section 11 timer v rev. 6.00 mar. 24, 2006 page 153 of 412 rej09b0142-0600 n ? 1 n + 1 n internal clock tcntv input clock tcntv figure 11.2 increment timi ng with internal clock n ? 1 n + 1 n tmciv (external clock input pin) tcntv input clock tcntv figure 11.3 increment timing with external clock h'ff h'00 tcntv overflow signal ovf figure 11.4 ovf set timing
section 11 timer v rev. 6.00 mar. 24, 2006 page 154 of 412 rej09b0142-0600 n n n+1 tcntv tcora or tcorb compare match signal cmfa or cmfb figure 11.5 cmfa and cmfb set timing compare match a signal timer v output pin figure 11.6 tmov output timing n h'00 compare match a signal tcntv figure 11.7 clear ti ming by compare match
section 11 timer v rev. 6.00 mar. 24, 2006 page 155 of 412 rej09b0142-0600 tmriv(external counter reset input pin ) tcntv reset signal tcntv n ? 1 n h'00 figure 11.8 clear ti ming by tmriv input 11.5 timer v application examples 11.5.1 pulse output with arbitrary duty cycle figure 11.9 shows an example of output of pulses with an arbitrary duty cycle. 1. set bits cclr1 and cclr0 in tcrv0 so that tcntv will be cleared by compare match with tcora. 2. set bits os3 to os0 in tcsrv so that the output will go to 1 at compare match with tcora and to 0 at compare match with tcorb. 3. set bits cks2 to cks0 in tcrv0 and bit icks 0 in tcrv1 to select the desired clock source. 4. with these settings, a waveform is output without further software intervention, with a period determined by tcora and a pulse width determined by tcorb. counter cleared time tcntv value h'ff tcora tcorb h'00 tmov figure 11.9 pulse output example
section 11 timer v rev. 6.00 mar. 24, 2006 page 156 of 412 rej09b0142-0600 11.5.2 pulse output with arbitrary pulse width and delay from trgv input the trigger function can be used to output a pulse with an arbitrary pulse width at an arbitrary delay from the trgv input, as shown in figure 11.10. to set up this output: 1. set bits cclr1 and cclr0 in tcrv0 so that tcntv will be cleared by compare match with tcorb. 2. set bits os3 to os0 in tcsrv so that the output will go to 1 at compare match with tcora and to 0 at compare match with tcorb. 3. set bits tveg1 and tveg0 in tcrv1 and set trge to select the falling edge of the trgv input. 4. set bits cks2 to cks0 in tcrv0 and bit icks0 in tcrv1 to select the desired clock source. 5. after these settings, a pulse waveform will be output without further software intervention, with a delay determined by tcora from the trgv input, and a pulse width determined by (tcorb ? tcora). counter cleared h'ff tcora tcorb h'00 trgv tmov compare match a compare match b clears tcntv and halts count-up compare match b clears tcntv and halts count-up compare match a tcntv value time figure 11.10 example of pulse ou tput synchronized to trgv input
section 11 timer v rev. 6.00 mar. 24, 2006 page 157 of 412 rej09b0142-0600 11.6 usage notes the following types of contention or operation can occur in timer v operation. 1. writing to registers is performed in the t3 state of a tcntv write cycle. if a tcntv clear signal is generated in the t3 state of a tcntv write cycle, as shown in figure 11.11, clearing takes precedence and the write to the counter is not carried out. if counting-up is generated in the t3 state of a tcntv write cy cle, writing takes precedence. 2. if a compare match is generated in the t3 st ate of a tcora or tcorb write cycle, the write to tcora or tcorb takes precedence and the compare match signal is inhibited. figure 11.12 shows the timing. 3. if compare matches a and b occur simultaneously, any conflict between the output selections for compare match a and compare match b is re solved by the following priority: toggle output > > address tcntv address tcntv write cycle by cpu internal write signal counter clear signal tcntv n h'00 t 1 t 2 t 3 figure 11.11 contention between tcntv write and clear
section 11 timer v rev. 6.00 mar. 24, 2006 page 158 of 412 rej09b0142-0600 address tcora address internal write signal tcntv tcora n n n+1 m tcora write data inhibited t 1 t 2 t 3 tcora write cycle by cpu compare match signal figure 11.12 contention betwee n tcora write and compare match clock before switching clock after switching count clock tcntv n n+1 n+2 write to cks1 and cks0 figure 11.13 internal clock switching and tcntv operation
section 12 timer w rev. 6.00 mar. 24, 2006 page 159 of 412 rej09b0142-0600 section 12 timer w the timer w has a 16-bit timer having output co mpare and input capture functions. the timer w can count external events and output pulses with an arbitrary duty cycle by compare match between the timer counter and four general registers. thus, it can be applied to various systems. 12.1 features ? selection of five counter clock sources: four internal clocks ( , /2, /4, and /8) and an external clock (external events can be counted) ? capability to process up to four pulse outputs or four pulse inputs ? four general registers: ? independently assignable output compare or input capture functions ? usable as two pairs of registers; one register of each pair operates as a buffer for the output compare or input capture register ? four selectable operating modes : ? waveform output by compare match selection of 0 output, 1 output, or toggle output ? input capture function rising edge, falling edge, or both edges ? counter clearing function counters can be cleared by compare match ? pwm mode up to three-phase pwm output can be provided with desired duty ratio. ? any initial timer output value can be set ? five interrupt sources four compare match/input capture interrupts and an overflow interrupt.
section 12 timer w rev. 6.00 mar. 24, 2006 page 160 of 412 rej09b0142-0600 table 12.1 summarizes the timer w functions, and figure 12.1 shows a block diagram of the timer w. table 12.1 timer w functions input/output pins item counter ftioa ftiob ftioc ftiod count clock internal clocks: , /2, /4, /8 external clock: ftci general registers (output compare/input capture registers) period specified in gra gra grb grc (buffer register for gra in buffer mode) grd (buffer register for grb in buffer mode) counter clearing function gra compare match gra compare match ? ? ? initial output value setting function ? yes yes yes yes buffer function ? yes yes ? ? compare 0 ? yes yes yes yes match output 1 ? yes yes yes yes toggle ? yes yes yes yes input capture function ? yes yes yes yes pwm mode ? ? yes yes yes interrupt sources overflow compare match/input capture compare match/input capture compare match/input capture compare match/input capture
section 12 timer w rev. 6.00 mar. 24, 2006 page 161 of 412 rej09b0142-0600 internal clock: external clock: ftci ftioa ftiob ftioc ftiod irrtw control logic clock selector comparator tcnt internal data bus bus interface [legend] tmrw: timer mode register w (8 bits) tcrw: timer control register w (8 bits) tierw: timer interrupt enable register w (8 bits) tsrw: timer status register w (8 bits) tior: timer i/o control register (8 bits) tcnt: timer counter (16 bits) gra: general register a (input capture/output compare register: 16 bits) grb: general register b (input capture/output compare register: 16 bits) grc: general register c (input capture/output compare register: 16 bits) grd: general register d (input capture/output compare register: 16 bits) irrtw: timer w interrupt request gra grb grc grd tmrw tcrw tierw tsrw tior /2 /4 /8 figure 12.1 timer w block diagram
section 12 timer w rev. 6.00 mar. 24, 2006 page 162 of 412 rej09b0142-0600 12.2 input/output pins table 12.2 summarizes the timer w pins. table 12.2 pin configuration name abbreviation input/output function external clock input ftci input external clock input pin input capture/output compare a ftioa input/output output pin for gra output compare or input pin for gra input capture input capture/output compare b ftiob input/output output pi n for grb output compare, input pin for grb input capture, or pwm output pin in pwm mode input capture/output compare c ftioc input/output output pi n for grc output compare, input pin for grc input capture, or pwm output pin in pwm mode input capture/output compare d ftiod input/output output pi n for grd output compare, input pin for grd input capture, or pwm output pin in pwm mode 12.3 register descriptions the timer w has the following registers. ? timer mode register w (tmrw) ? timer control register w (tcrw) ? timer interrupt enable register w (tierw) ? timer status register w (tsrw) ? timer i/o control register 0 (tior0) ? timer i/o control register 1 (tior1) ? timer counter (tcnt) ? general register a (gra) ? general register b (grb) ? general register c (grc) ? general register d (grd)
section 12 timer w rev. 6.00 mar. 24, 2006 page 163 of 412 rej09b0142-0600 12.3.1 timer mode register w (tmrw) tmrw selects the general register functions and the timer output mode. bit bit name initial value r/w description 7 cts 0 r/w counter start the counter operation is halted when this bit is 0, while it can be performed when this bit is 1. 6 ? 1 ? reserved this bit is always read as 1. 5 bufeb 0 r/w buffer operation b selects the grd function. 0: grd operates as an input capture/output compare register 1: grd operates as the buffer register for grb 4 bufea 0 r/w buffer operation a selects the grc function. 0: grc operates as an input capture/output compare register 1: grc operates as the buffer register for gra 3 ? 1 ? reserved this bit is always read as 1. 2 pwmd 0 r/w pwm mode d selects the output mode of the ftiod pin. 0: ftiod operates normally (output compare output) 1: pwm output 1 pwmc 0 r/w pwm mode c selects the output mode of the ftioc pin. 0: ftioc operates normally (output compare output) 1: pwm output 0 pwmb 0 r/w pwm mode b selects the output mode of the ftiob pin. 0: ftiob operates normally (output compare output) 1: pwm output
section 12 timer w rev. 6.00 mar. 24, 2006 page 164 of 412 rej09b0142-0600 12.3.2 timer control register w (tcrw) tcrw selects the timer counter clock source, sel ects a clearing condition, and specifies the timer output levels. bit bit name initial value r/w description 7 cclr 0 r/w counter clear the tcnt value is cleared by compare match a when this bit is 1. when it is 0, tcnt operates as a free- running counter. 6 5 4 cks2 cks1 cks0 0 0 0 r/w r/w r/w clock select 2 to 0 select the tcnt clock source. 000: internal clock: counts on 001: internal clock: counts on /2 010: internal clock: counts on /4 011: internal clock: counts on /8 1xx: counts on rising edges of the external event (ftci) when the internal clock source ( ) is selected, subclock sources are counted in subactive and subsleep modes. 3 tod 0 r/w timer output level setting d sets the output value of t he ftiod pin until the first compare match d is generated. 0: output value is 0 * 1: output value is 1 * 2 toc 0 r/w timer output level setting c sets the output value of t he ftioc pin until the first compare match c is generated. 0: output value is 0 * 1: output value is 1 * 1 tob 0 r/w timer output level setting b sets the output value of t he ftiob pin until the first compare match b is generated. 0: output value is 0 * 1: output value is 1 *
section 12 timer w rev. 6.00 mar. 24, 2006 page 165 of 412 rej09b0142-0600 bit bit name initial value r/w description 0 toa 0 r/w timer output level setting a sets the output value of t he ftioa pin until the first compare match a is generated. 0: output value is 0 * 1: output value is 1 * [legend] x: don't care. note: * the change of the setting is immediat ely reflected in the output value. 12.3.3 timer interrupt en able register w (tierw) tierw controls the timer w interrupt request. bit bit name initial value r/w description 7 ovie 0 r/w timer overflow interrupt enable when this bit is set to 1, fovi interrupt requested by ovf flag in tsrw is enabled. 6 5 4 ? ? ? 1 1 1 ? ? ? reserved these bits are always read as 1. 3 imied 0 r/w input capture/com pare match interrupt enable d when this bit is set to 1, imid interrupt requested by imfd flag in tsrw is enabled. 2 imiec 0 r/w input capture/com pare match interrupt enable c when this bit is set to 1, imic interrupt requested by imfc flag in tsrw is enabled. 1 imieb 0 r/w input capture/com pare match interrupt enable b when this bit is set to 1, imib interrupt requested by imfb flag in tsrw is enabled. 0 imiea 0 r/w input capture/com pare match interrupt enable a when this bit is set to 1, imia interrupt requested by imfa flag in tsrw is enabled.
section 12 timer w rev. 6.00 mar. 24, 2006 page 166 of 412 rej09b0142-0600 12.3.4 timer status register w (tsrw) tsrw shows the status of interrupt requests. bit bit name initial value r/w description 7 ovf 0 r/w timer overflow flag [setting condition] when tcnt overflows from h'ffff to h'0000 [clearing condition] read ovf when ovf = 1, then write 0 in ovf 6 5 4 ? ? ? 1 1 1 ? ? ? reserved these bits are always read as 1. 3 imfd 0 r/w input capt ure/compare match flag d [setting conditions] ? tcnt = grd when grd functions as an output compare register ? the tcnt value is transferred to grd by an input capture signal when grd functions as an input capture register [clearing condition] read imfd when imfd = 1, then write 0 in imfd 2 imfc 0 r/w input capt ure/compare match flag c [setting conditions] ? tcnt = grc when grc functions as an output compare register ? the tcnt value is transferred to grc by an input capture signal when grc functions as an input capture register [clearing condition] read imfc when imfc = 1, then write 0 in imfc
section 12 timer w rev. 6.00 mar. 24, 2006 page 167 of 412 rej09b0142-0600 bit bit name initial value r/w description 1 imfb 0 r/w input capt ure/compare match flag b [setting conditions] ? tcnt = grb when grb functions as an output compare register ? the tcnt value is transferred to grb by an input capture signal when grb functions as an input capture register [clearing condition] read imfb when imfb = 1, then write 0 in imfb 0 imfa 0 r/w input capt ure/compare match flag a [setting conditions] ? tcnt = gra when gra functions as an output compare register ? the tcnt value is transferred to gra by an input capture signal when gra functions as an input capture register [clearing condition] read imfa when imfa = 1, then write 0 in imfa 12.3.5 timer i/o control register 0 (tior0) tior0 selects the functions of gra and grb, and specifies the functions of the ftioa and ftiob pins. bit bit name initial value r/w description 7 ? 1 ? reserved this bit is always read as 1. 6 iob2 0 r/w i/o control b2 selects the grb function. 0: grb functions as an output compare register 1: grb functions as an input capture register
section 12 timer w rev. 6.00 mar. 24, 2006 page 168 of 412 rej09b0142-0600 bit bit name initial value r/w description 5 4 iob1 iob0 0 0 r/w r/w i/o control b1 and b0 when iob2 = 0, 00: no output at compare match 01: 0 output to the ftiob pin at grb compare match 10: 1 output to the ftiob pin at grb compare match 11: output toggles to the ftiob pin at grb compare match when iob2 = 1, 00: input capture at risi ng edge at the ftiob pin 01: input capture at fallin g edge at the ftiob pin 1x: input capture at rising and falling edges of the ftiob pin 3 ? 1 ? reserved this bit is always read as 1. 2 ioa2 0 r/w i/o control a2 selects the gra function. 0: gra functions as an output compare register 1: gra functions as an input capture register 1 0 ioa1 ioa0 0 0 r/w r/w i/o control a1 and a0 when ioa2 = 0, 00: no output at compare match 01: 0 output to the ftioa pin at gra compare match 10: 1 output to the ftioa pin at gra compare match 11: output toggles to the ftioa pin at gra compare match when ioa2 = 1, 00: input capture at risi ng edge of the ftioa pin 01: input capture at fallin g edge of the ftioa pin 1x: input capture at rising and falling edges of the ftioa pin [legend] x: don't care.
section 12 timer w rev. 6.00 mar. 24, 2006 page 169 of 412 rej09b0142-0600 12.3.6 timer i/o control register 1 (tior1) tior1 selects the functions of grc and grd, and specifies the functions of the ftioc and ftiod pins. bit bit name initial value r/w description 7 ? 1 ? reserved this bit is always read as 1. 6 iod2 0 r/w i/o control d2 selects the grd function. 0: grd functions as an output compare register 1: grd functions as an input capture register 5 4 iod1 iod0 0 0 r/w r/w i/o control d1 and d0 when iod2 = 0, 00: no output at compare match 01: 0 output to the ftiod pin at grd compare match 10: 1 output to the ftiod pin at grd compare match 11: output toggles to the ftiod pin at grd compare match when iod2 = 1, 00: input capture at risi ng edge at the ftiod pin 01: input capture at fallin g edge at the ftiod pin 1x: input capture at rising and falling edges at the ftiod pin 3 ? 1 ? reserved this bit is always read as 1. 2 ioc2 0 r/w i/o control c2 selects the grc function. 0: grc functions as an output compare register 1: grc functions as an input capture register
section 12 timer w rev. 6.00 mar. 24, 2006 page 170 of 412 rej09b0142-0600 bit bit name initial value r/w description 1 0 ioc1 ioc0 0 0 r/w r/w i/o control c1 and c0 when ioc2 = 0, 00: no output at compare match 01: 0 output to the ftioc pin at grc compare match 10: 1 output to the ftioc pin at grc compare match 11: output toggles to the ftioc pin at grc compare match when ioc2 = 1, 00: input capture to grc at rising edge of the ftioc pin 01: input capture to grc at falling edge of the ftioc pin 1x: input capture to grc at rising and falling edges of the ftioc pin [legend] x: don't care. 12.3.7 timer counter (tcnt) tcnt is a 16-bit readable/writable up-counter. th e clock source is selected by bits cks2 to cks0 in tcrw. tcnt can be cleared to h'0000 through a compare match with gra by setting the cclr in tcrw to 1. when tcnt overflows (changes from h'ffff to h'0000), the ovf flag in tsrw is set to 1. if ovie in tierw is set to 1 at this time, an interrupt request is generated. tcnt must always be read or wri tten in 16-bit units; 8-bit access is not allowed. tcnt is initialized to h'0000 by a reset.
section 12 timer w rev. 6.00 mar. 24, 2006 page 171 of 412 rej09b0142-0600 12.3.8 general registers a to d (gra to grd) each general register is a 16-bit readable/writable register that can function as either an output- compare register or an input-capture register. the function is selected by settings in tior0 and tior1. when a general register is used as an input-compare register, its value is constantly compared with the tcnt value. when the two values match (a compare match), the corresponding flag (imfa, imfb, imfc, or imfd) in tsrw is set to 1. an in terrupt request is generated at this time, when imiea, imieb, imiec, or imied is set to 1. compare match output can be selected in tior. when a general register is used as an input-captu re register, an external input-capture signal is detected and the current tcnt value is stored in the general register. the corresponding flag (imfa, imfb, imfc, or imfd) in tsrw is set to 1. if the corresponding interrupt-enable bit (imiea, imieb, imiec, or imied) in tsrw is se t to 1 at this time, an interrupt request is generated. the edge of the input-cap ture signal is selected in tior. grc and grd can be used as buffer registers of gra and grb, respectively, by setting bufea and bufeb in tmrw. for example, when gra is set as an output-compare register and grc is set as the buffer register for gra, the value in the buffer register grc is sent to gra whenever compare match a is generated. when gra is set as an input-capture register and grc is set as the buffer register for gra, the value in tcnt is transferred to gra and the valu e in the buffer register grc is transferred to gra whenever an input capture is generated. gra to grd must be written or read in 16-bit un its; 8-bit access is not a llowed. gra to grd are initialized to h'ffff by a reset.
section 12 timer w rev. 6.00 mar. 24, 2006 page 172 of 412 rej09b0142-0600 12.4 operation the timer w has the following operating modes. ? normal operation ? pwm operation 12.4.1 normal operation tcnt performs free-running or periodic counting operations. after a reset, tcnt is set as a free- running counter. when the cts bit in tmrw is se t to 1, tcnt starts incrementing the count. when the count overflows from h'ffff to h'0000, the ovf flag in tsrw is set to 1. if the ovie in tierw is set to 1, an interrupt request is ge nerated. figure 12.2 shows free-running counting. tcnt value h'ffff h'0000 cts bit ovf time flag cleared by software figure 12.2 free-running counter operation periodic counting operation can be performed when gra is set as an output compare register and bit cclr in tcrw is set to 1. when the count matches gra, tcnt is cleared to h'0000, the imfa flag in tsrw is set to 1. if the correspond ing imiea bit in tierw is set to 1, an interrupt request is generated. tcnt continues counting from h'0000. figure 12.3 shows periodic counting.
section 12 timer w rev. 6.00 mar. 24, 2006 page 173 of 412 rej09b0142-0600 tcnt value gra h'0000 cts bit imfa time flag cleared by software figure 12.3 periodic counter operation by setting a general register as an output comp are register, compare matc h a, b, c, or d can cause the output at the ftioa, ftiob, ftioc, or ftiod pin to output 0, output 1, or toggle. figure 12.4 shows an example of 0 and 1 output when tcnt operates as a free-running counter, 1 output is selected for compare match a, and 0 output is selected for compare match b. when signal is already at the selected output level, the signal level does not ch ange at compare match. tcnt value h'ffff h'0000 ftioa ftiob time gra grb no change no change no change no change figure 12.4 0 and 1 output example (toa = 0, tob = 1)
section 12 timer w rev. 6.00 mar. 24, 2006 page 174 of 412 rej09b0142-0600 figure 12.5 shows an example of toggle output when tcnt operates as a free-running counter, and toggle output is selected for both compare match a and b. tcnt value h'ffff h'0000 ftioa ftiob time gra grb toggle output toggle output figure 12.5 toggle output example (toa = 0, tob = 1) figure 12.6 shows another example of toggle output when tcnt operates as a periodic counter, cleared by compare matc h a. toggle output is selected for both compare match a and b. tcnt value h'ffff h'0000 ftioa ftiob time gra grb toggle output toggle output counter cleared by compare match with gra figure 12.6 toggle output example (toa = 0, tob = 1)
section 12 timer w rev. 6.00 mar. 24, 2006 page 175 of 412 rej09b0142-0600 the tcnt value can be captured into a general register (gra, grb, grc, or grd) when a signal level changes at an input-capture pin (ftioa, ftiob, ftioc, or ftiod). capture can take place on the rising edge, fal ling edge, or both edges. by usin g the input-capture function, the pulse width and periods can be measured. figure 12.7 shows an example of input capture when both edges of ftioa and the falling edge of ftiob are selected as capture edges. tcnt operates as a free-running counter. tcnt value h'ffff h'1000 h'0000 ftioa gra time h'aa55 h'55aa h'f000 h'1000 h'f000 h'55aa grb h'aa55 ftiob figure 12.7 input capture operating example
section 12 timer w rev. 6.00 mar. 24, 2006 page 176 of 412 rej09b0142-0600 figure 12.8 shows an example of buffer operation when the gra is set as an input-capture register and grc is set as the bu ffer register for gra. tcnt op erates as a free-running counter, and ftioa captures both rising and falling edge of the input signal. due to the buffer operation, the gra value is transferred to grc by input-cap ture a and the tcnt value is stored in gra. tcnt value h'da91 h'0245 h'0000 grc time h'0245 ftioa gra h'5480 h'0245 h'ffff h'5480 h'5480 h'da91 figure 12.8 buffer operation example (input capture) 12.4.2 pwm operation in pwm mode, pwm waveforms are generated by using gra as the period register and grb, grc, and grd as duty registers. pwm waveforms are output from the ftiob, ftioc, and ftiod pins. up to three-phase pwm waveforms can be output. in pwm mode, a general register functions as an output compare register automatically. the out put level of each pin depends on the corresponding timer output level set bit (tob, toc, and tod) in tcrw. when tob is 1, the ftiob output goes to 1 at compare match a and to 0 at compare match b. when tob is 0, the ftiob output goes to 0 at compare match a and to 1 at compare match b. thus the compare match output level settings in tior0 and tior1 are ignored for the output pin set to pwm mode. if the same value is set in the cycle register and the duty register, the output does not change when a compare match occurs.
section 12 timer w rev. 6.00 mar. 24, 2006 page 177 of 412 rej09b0142-0600 figure 12.9 shows an example of operation in pwm mode. the output signals go to 1 and tcnt is cleared at compare match a, and the output signals go to 0 at compare match b, c, and d (tob, toc, and tod = 1: initial output values are set to 1). tcnt value gra grb grc h'0000 ftiob ftioc ftiod time grd counter cleared by compare match a figure 12.9 pwm mode example (1) figure 12.10 shows another example of operation in pwm mode. the output signals go to 0 and tcnt is cleared at compare match a, and the output signals go to 1 at compare match b, c, and d (tob, toc, and tod = 0: initial output values are set to 1). tcnt value gra grb grc h'0000 ftiob ftioc ftiod time grd counter cleared by compare match a figure 12.10 pwm mode example (2)
section 12 timer w rev. 6.00 mar. 24, 2006 page 178 of 412 rej09b0142-0600 figure 12.11 shows an example of buffer opera tion when the ftiob pin is set to pwm mode and grd is set as the buffer register for grb. tc nt is cleared by compare match a, and ftiob outputs 1 at compare match b and 0 at compare match a. due to the buffer operation, the ftiob output level changes and the value of buffer register grd is transferred to grb whenever compare match b occurs. this pr ocedure is repeated every time compare match b occurs. tcnt value gra h'0000 grd time grb h'0200 h'0520 ftiob h'0200 h'0450 h'0520 h'0450 grb h'0450 h'0520 h'0200 figure 12.11 buffer operatio n example (output compare)
section 12 timer w rev. 6.00 mar. 24, 2006 page 179 of 412 rej09b0142-0600 figures 12.12 and 12.13 show examples of the output of pwm waveforms with duty cycles of 0% and 100%. tcnt value gra h'0000 ftiob time grb duty 0% write to grb write to grb tcnt value gra h'0000 ftiob time grb duty 100% write to grb write to grb output does not change when cycle register and duty register compare matches occur simultaneously. tcnt value gra h'0000 ftiob time grb duty 100% write to grb write to grb write to grb output does not change when cycle register and duty register compare matches occur simultaneously. duty 0% write to grb figure 12.12 pwm mode example (tob, toc, and tod = 0: initial output values are set to 0)
section 12 timer w rev. 6.00 mar. 24, 2006 page 180 of 412 rej09b0142-0600 tcnt value gra h'0000 ftiob time grb duty 100% write to grb tcnt value gra h'0000 ftiob time grb duty 0% write to grb write to grb output does not change when cycle register and duty register compare matches occur simultaneously. tcnt value gra h'0000 ftiob time grb duty 0% write to grb write to grb output does not change when cycle register and duty register compare matches occur simultaneously. duty 100% write to grb write to grb write to grb figure 12.13 pwm mode example (tob, toc, and tod = 1: initial output values are set to 1)
section 12 timer w rev. 6.00 mar. 24, 2006 page 181 of 412 rej09b0142-0600 12.5 operation timing 12.5.1 tcnt count timing figure 12.14 shows the tcnt count timing when th e internal clock source is selected. figure 12.15 shows the timing when the ex ternal clock source is selected. the pulse width of the external clock signal must be at least two system clock ( ) cycles; shorter pulses will not be counted correctly. tcnt tcnt input clock internal clock n n+1 n+2 rising edge figure 12.14 count timing for internal clock source tcnt tcnt input clock external clock nn+1 n+2 rising edge rising edge figure 12.15 count timing for external clock source
section 12 timer w rev. 6.00 mar. 24, 2006 page 182 of 412 rej09b0142-0600 12.5.2 output comp are output timing the compare match signal is generated in the last state in which tcnt and gr match (when tcnt changes from the matching value to the next value). when the compare match signal is generated, the output value selected in tior is output at the compare match output pin (ftioa, ftiob, ftioc, or ftiod). when tcnt matches gr, the compare match signal is generated only after the next counter clock pulse is input. figure 12.16 shows the output compare timing. gra to grd tcnt tcnt input clock n n n+1 compare match signal ftioa to ftiod figure 12.16 output compare output timing
section 12 timer w rev. 6.00 mar. 24, 2006 page 183 of 412 rej09b0142-0600 12.5.3 input ca pture timing input capture on the rising edge, falling edge, or both edges can be selected through settings in tior0 and tior1. figure 12.17 shows the timing when the falling edge is selected. the pulse width of the input capture signal mu st be at least two system clock ( ) cycles; shorter pulses will not be detected correctly. tcnt input capture input n?1 n n+1 n+2 n gra to grd input capture signal figure 12.17 input capture input signal timing 12.5.4 timing of counter clearing by compare match figure 12.18 shows the timing when the counter is cleared by compare match a. when the gra value is n, the counter counts from 0 to n, and its cycle is n + 1. tcnt compare match signal gra n n h'0000 figure 12.18 timing of count er clearing by compare match
section 12 timer w rev. 6.00 mar. 24, 2006 page 184 of 412 rej09b0142-0600 12.5.5 buffer operation timing figures 12.19 and 12.20 show the buffer operation timing. grc, grd compare match signal tcnt gra, grb n n+1 m m figure 12.19 buffer operat ion timing (compare match) gra, grb tcnt input capture signal grc, grd n m m n+1 n n n+1 figure 12.20 buffer operat ion timing (input capture)
section 12 timer w rev. 6.00 mar. 24, 2006 page 185 of 412 rej09b0142-0600 12.5.6 timing of imfa to imfd flag setting at compare match if a general register (gra, grb, grc, or grd) is used as an output compare register, the corresponding imfa, imfb, imfc, or imfd flag is set to 1 when tcnt matches the general register. the compare match signal is generated in the last state in which the values match (when tcnt is updated from the matching count to the next count). therefore, when tcnt matches a general register, the compare match signal is generated only after the next tcnt clock pulse is input. figure 12.21 shows the timing of the imfa to imfd flag setting at compare match. gra to grd tcnt tcnt input clock n n n+1 compare match signal imfa to imfd irrtw figure 12.21 timing of imfa to imfd flag setting at compare match
section 12 timer w rev. 6.00 mar. 24, 2006 page 186 of 412 rej09b0142-0600 12.5.7 timing of imfa to im fd setting at input capture if a general register (gra, grb, grc, or grd) is used as an input capture register, the corresponding imfa, imfb, imfc, or imfd flag is set to 1 when an input capture occurs. figure 12.22 shows the timing of the imfa to imfd flag setting at input capture. gra to grd tcnt input capture signal n n imfa to imfd irrtw figure 12.22 timing of imfa to imfd flag setting at input capture 12.5.8 timing of st atus flag clearing when the cpu reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag is cleared. figure 12.23 shows th e status flag clearing timing. imfa to imfd write signal address tsrw address irrtw tsrw write cycle t1 t2 figure 12.23 timing of status flag clearing by cpu
section 12 timer w rev. 6.00 mar. 24, 2006 page 187 of 412 rej09b0142-0600 12.6 usage notes the following types of contention or operation can occur in timer w operation. 1. the pulse width of the input clock signal and the input capture signal must be at least two system clock ( ) cycles; shorter pulses will not be detected correctly. 2. writing to registers is performed in the t2 state of a tcnt write cycle. if counter clear signal occurs in the t2 state of a tcnt write cycle, clearing of the counter takes priority and the write is not performed, as shown in figure 12.24. if counting-up is generated in the tcnt write cycle to contend with the tcnt counting-up, writing takes precedence. 3. depending on the timing, tcnt may be incremented by a switch between different internal clock sources. when tcnt is internally clocked, an increment pulse is generated from the rising edge of an internal clock signal, that is divided system clock ( ). therefore, as shown in figure 12.25 the switch is from a low clock signal to a high clock signal, the switchover is seen as a rising edge, causing tcnt to increment. 4. if timer w enters module standby mode while an interrupt request is generated, the interrupt request cannot be cleared. before entering mo dule standby mode, disable interrupt requests. counter clear signal write signal address tcnt address tcnt tcnt write cycle t1 t2 n h'0000 figure 12.24 contention between tcnt write and clear
section 12 timer w rev. 6.00 mar. 24, 2006 page 188 of 412 rej09b0142-0600 tcnt previous clock n n+1 n+2 n+3 new clock count clock the change in signal level at clock switching is assumed to be a rising edge, and tcnt increments the count. figure 12.25 internal clock switching and tcnt operation 5. the toa to tod bits in tcrw decide the value of the ftio pin, which is output until the first compare match occurs. once a compare matc h occurs and this comp are match changes the values of ftioa to ftiod output, the values of the ftioa to ftiod pin output and the values read from the toa to tod bits may differ. moreover, when the writing to tcrw and the generation of the compare match a to d o ccur at the same timing, the writing to tcrw has the priority. thus, output change due to the compare match is not reflected to the ftioa to ftiod pins. therefore, when bit manipulation instruction is used to write to tcrw, the values of the ftioa to ftiod pin output may result in an unexpected result. when tcrw is to be written to while compare match is opera ting, stop the counter once before accessing to tcrw, read the port 8 state to reflect the valu es of ftioa to ftiod output, to toa to tod, and then restart the counter. figure 12.26 sh ows an example when the compare match and the bit manipulation instruction to tcrw occur at the same timing.
section 12 timer w rev. 6.00 mar. 24, 2006 page 189 of 412 rej09b0142-0600 compare match b signal ftiob pin tcrw write signal set value bit trccr1 0 cclr 0 cks2 0 cks1 0 cks0 0 tod 1 toc 1 tob 0 765 43210 toa expected output remains high because the writing 1 to tob has priority tcrw has been set to h'06. compare match b and compare match c are used. the ftiob pin is the 1 output state, and is set to the toggle output or the 0 output on compare match b. when bclr#2, @tcrw is executed to clear the toc bit (the ftioc signal is low) and compare match b occurs at the same timing as shown below, the h'02 writing to tcrw has priority and compare match b does not drive the ftiob signal low; the ftiob signal remains high. bclr#2, @tcrw (1) tcrw read operation: read h'06 (2) modify operation: modify h'06 to h'02 (3) write operation to tcrw: write h'02 figure 12.26 when compa re match and bit manipulation instruction to tcrw occur at the same timing
section 12 timer w rev. 6.00 mar. 24, 2006 page 190 of 412 rej09b0142-0600
section 13 watchdog timer rev. 6.00 mar. 24, 2006 page 191 of 412 rej09b0142-0600 section 13 watchdog timer the watchdog timer is an 8-bit timer that can gene rate an internal reset signal for this lsi if a system crash prevents the cpu from writing to th e timer counter, thus allowing it to overflow. the block diagram of the watchdog timer is shown in figure 13.1. internal reset signal pss tcwd tmwd tcsrwd internal data bus [legend] tcsrwd: timer control/status register wd tcwd: timer counter wd pss: prescaler s tmwd: timer mode register wd internal oscillator clk figure 13.1 block diagram of watchdog timer 13.1 features ? ? 13.2 register descriptions the watchdog timer has the following registers. ? ? ?
section 13 watchdog timer rev. 6.00 mar. 24, 2006 page 192 of 412 rej09b0142-0600 13.2.1 timer control/stat us register wd (tcsrwd) tcsrwd performs the tcsrwd and tcwd writ e control. tcsrwd also controls the watchdog timer operation and indicates the operatin g state. tcsrwd must be rewritten by using the mov instruction. the bit manipulation instruction cannot be used to change the setting value. bit bit name initial value r/w description 7 b6wi 1 r/w bit 6 write inhibit the tcwe bit can be written only when the write value of the b6wi bit is 0. this bit is always read as 1. 6 tcwe 0 r/w timer counter wd write enable tcwd can be written when the tcwe bit is set to 1. when writing data to this bit, the value for bit 7 must be 0. 5 b4wi 1 r/w bit 4 write inhibit the tcsrwe bit can be written only when the write value of the b4wi bit is 0. this bit is always read as 1. 4 tcsrwe 0 r/w timer control/status register wd write enable the wdon and wrst bits can be written when the tcsrwe bit is set to 1. when writing data to this bit, the value for bit 5 must be 0. 3 b2wi 1 r/w bit 2 write inhibit this bit can be written to the wdon bit only when the write value of the b2wi bit is 0. this bit is always read as 1.
section 13 watchdog timer rev. 6.00 mar. 24, 2006 page 193 of 412 rej09b0142-0600 bit bit name initial value r/w description 2 wdon 0 r/w watchdog timer on tcwd starts counting up when wdon is set to 1 and halts when wdon is cleared to 0. [setting condition] when 1 is written to the wdon bit while writing 0 to the b2wi bit when the tcsrwe bit=1 [clearing conditions] ? reset by res pin ? when 0 is written to the wdon bit while writing 0 to the b2wi when the tcsrwe bit=1 1 b0wi 1 r/w bit 0 write inhibit this bit can be written to the wrst bit only when the write value of the b0wi bit is 0. this bit is always read as 1. 0 wrst 0 r/w watchdog timer reset [setting condition] when tcwd overflows and an internal reset signal is generated [clearing conditions] ? reset by res pin ? when 0 is written to the wrst bit while writing 0 to the b0wi bit when the tcsrwe bit=1 13.2.2 timer coun ter wd (tcwd) tcwd is an 8-bit readable/writable up-counter. when tcwd overflows from h'ff to h'00, the internal reset signal is generated and the wrst bit in tcsrwd is set to 1. tcwd is initialized to h'00.
section 13 watchdog timer rev. 6.00 mar. 24, 2006 page 194 of 412 rej09b0142-0600 13.2.3 timer mode register wd (tmwd) tmwd selects the input clock. bit bit name initial value r/w description 7 to 4 ? all 1 ? reserved these bits are always read as 1. 3 2 1 0 cks3 cks2 cks1 cks0 1 1 1 1 r/w r/w r/w r/w clock select 3 to 0 select the clock to be input to tcwd. 1000: internal clock: counts on /64 1001: internal clock: counts on /128 1010: internal clock: counts on /256 1011: internal clock: counts on /512 1100: internal clock: counts on /1024 1101: internal clock: counts on /2048 1110: internal clock: counts on /4096 1111: internal clock: counts on 8192 0xxx: internal oscillator for the internal oscillator overflow periods, see section 20, electrical characteristics. [legend] x: don't care.
section 13 watchdog timer rev. 6.00 mar. 24, 2006 page 195 of 412 rej09b0142-0600 13.3 operation the watchdog timer is provided with an 8-bit counter. if 1 is written to wdon while writing 0 to b2wi when the tcsrwe bit in tcsrwd is set to 1, tcwd begins counting up. (to operate the watchdog timer, two write accesses to tcsrwd are required.) when a clock pulse is input after the tcwd count value has reached h'ff, the watchdog timer overflows and an internal reset signal is generated. the internal reset signal is output for a period of 256 example: with 30ms overflow period when = 4 mhz 4 10 6 30 10 ?3 = 14.6 8192 tcwd overflow h'ff h'00 internal reset signal h'f1 tcwd count value h'f1 written to tcwd h'f1 written to tcwd reset generated start 256 osc clock cycles therefore, 256 ? 15 = 241 (h'f1) is set in tcw. figure 13.2 watchdog timer operation example
section 13 watchdog timer rev. 6.00 mar. 24, 2006 page 196 of 412 rej09b0142-0600
section 14 serial communication interface 3 (sci3) rev. 6.00 mar. 24, 2006 page 197 of 412 rej09b0142-0600 section 14 serial communi cation interface 3 (sci3) serial communication interface 3 (sci3) can handle both asynchronous and clocked synchronous serial communication. in the asyn chronous method, serial data communication can be carried out using standard asynchronous communication chips such as a universal asynchronous receiver/transmitter (uart) or an asynchronou s communication interface adapter (acia). a function is also provided for serial commun ication between processors (multiprocessor communication function). figure 14.1 shows a block diagram of the sci3. 14.1 features ? choice of asynchronous or clocked synchronous serial communication mode ? full-duplex communication capability the transmitter and receiver are mutually independ ent, enabling transmission and reception to be executed simultaneously. double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data. ? on-chip baud rate generator allows any bit rate to be selected ? external clock or on-chip baud rate generator can be selected as a transfer clock source. ? six interrupt sources transmit-end, transmit-data-empty , receive-data-full, ove rrun error, framing error, and parity error. asynchronous mode ? data length: 7 or 8 bits ? stop bit length: 1 or 2 bits ? parity: even, odd, or none ? receive error detection: parity , overrun, and framing errors ? break detection: break can be detected by read ing the rxd pin level directly in the case of a framing error clocked synchronous mode ? data length: 8 bits ? receive error detection: overrun errors detected
section 14 serial communication interface 3 (sci3) rev. 6.00 mar. 24, 2006 page 198 of 412 rej09b0142-0600 clock txd rxd sck 3 brr smr scr3 ssr tdr rdr tsr rsr transmit/receive control circuit internal data bus [legend] rsr: rdr: tsr: tdr: smr: scr3: ssr: brr: brc: receive shift register receive data register transmit shift register transmit data register serial mode register serial control register 3 serial status register bit rate register bit rate counter interrupt request (tei, txi, rxi, eri) internal clock ( /64, /16, /4, ) external clock brc baud rate generator figure 14.1 block diagram of sci3 14.2 input/output pins table 14.1 shows the sci3 pin configuration. table 14.1 pin configuration pin name abbreviation i/o function sci3 clock sck3 i/o sc i3 clock input/output sci3 receive data input rxd i nput sci3 receive data input sci3 transmit data output txd output sci3 transmit data output
section 14 serial communication interface 3 (sci3) rev. 6.00 mar. 24, 2006 page 199 of 412 rej09b0142-0600 14.3 register descriptions the sci3 has the following registers. ? receive shift register (rsr) ? receive data register (rdr) ? transmit shift register (tsr) ? transmit data register (tdr) ? serial mode register (smr) ? serial control register 3 (scr3) ? serial status register (ssr) ? bit rate register (brr) 14.3.1 receive shi ft register (rsr) rsr is a shift register that is us ed to receive serial data input fr om the rxd pin and convert it into parallel data. when one byte of data has been r eceived, it is transferred to rdr automatically. rsr cannot be directly accessed by the cpu. 14.3.2 receive data register (rdr) rdr is an 8-bit register that stores received data . when the sci3 has received one byte of serial data, it transfers the received serial data from rsr to rdr, where it is stored. after this, rsr is receive-enabled. as rsr and rdr function as a d ouble buffer in this way, continuous receive operations are possible. after confirming that the rdrf bit in ssr is set to 1, read rdr only once. rdr cannot be written to by the cpu. rdr is initialized to h'00. 14.3.3 transmit shift register (tsr) tsr is a shift register that transmits serial data. to perform serial data transmission, the sci3 first transfers transmit data fr om tdr to tsr automatically, then sends the data that starts from the lsb to the txd pin . tsr cannot be directly accessed by the cpu.
section 14 serial communication interface 3 (sci3) rev. 6.00 mar. 24, 2006 page 200 of 412 rej09b0142-0600 14.3.4 transmit data register (tdr) tdr is an 8-bit register that stores data for transmission. when the sc i3 detects that tsr is empty, it transfers the tr ansmit data written in tdr to tsr an d starts transmission. the double- buffered structure of tdr and tsr enables continuous serial transmission. if the next transmit data has already been written to tdr during transm ission of one-frame data, the sci3 transfers the written data to tsr to continue transmission. to achieve reliable serial transmission, write transmit data to tdr only once after confirming th at the tdre bit in ssr is set to 1. tdr is initialized to h'ff. 14.3.5 serial mode register (smr) smr is used to set the sci3?s serial transfer fo rmat and select the on-chip baud rate generator clock source. bit bit name initial value r/w description 7 com 0 r/w communication mode 0: asynchronous mode 1: clocked synchronous mode 6 chr 0 r/w character length (enabled only in asynchronous mode) 0: selects 8 bits as the data length. 1: selects 7 bits as the data length. 5 pe 0 r/w parity enable (enabled only in asynchronous mode) when this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. 4 pm 0 r/w parity mode (enabled only when the pe bit is 1 in asynchronous mode) 0: selects even parity. 1: selects odd parity.
section 14 serial communication interface 3 (sci3) rev. 6.00 mar. 24, 2006 page 201 of 412 rej09b0142-0600 bit bit name initial value r/w description 3 stop 0 r/w stop bit length (enabled only in asynchronous mode) selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits for reception, only the first stop bit is checked, regardless of the value in the bit. if the second stop bit is 0, it is treated as the start bit of the next transmit character. 2 mp 0 r/w multiprocessor mode when this bit is set to 1, the multiprocessor communication function is enabled. the pe bit and pm bit settings are invalid. in clocked synchronous mode, this bit should be cleared to 0. 1 0 cks1 cks0 0 0 r/w r/w clock select 0 and 1 these bits select the clock source for the on-chip baud rate generator. 00: clock (n = 0) 01: /4 clock (n = 1) 10: /16 clock (n = 2) 11: /64 clock (n = 3) for the relationship between the bit rate register setting and the baud rate, see section 14.3.8, bit rate register (brr). n is the dec imal representation of the value of n in brr (see section 14.3.8, bit rate register (brr)). 14.3.6 serial control register 3 (scr3) scr3 is a register that enables or disables sci3 transfer operations and interrupt requests, and is also used to select the transfer clock source. for details on interrupt requests, refer to section 14.7, interrupts. bit bit name initial value r/w description 7 tie 0 r/w transmit interrupt enable when this bit is set to 1, the txi interrupt request is enabled.
section 14 serial communication interface 3 (sci3) rev. 6.00 mar. 24, 2006 page 202 of 412 rej09b0142-0600 bit bit name initial value r/w description 6 rie 0 r/w receive interrupt enable when this bit is set to 1, rxi and eri interrupt requests are enabled. 5 te 0 r/w transmit enable when this bit is set to 1, transmission is enabled. 4 re 0 r/w receive enable when this bit is set to 1, reception is enabled. 3 mpie 0 r/w multiprocessor interrupt enable (enabled only when the mp bit in smr is 1 in asynchronous mode) when this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the rdrf, fer, and oer status flags in ssr is prohibited. on receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed. for details, refer to section 14.6, multipro cessor communication function. 2 teie 0 r/w transmit end interrupt enable when this bit is set to 1, the tei interrupt request is enabled. 1 0 cke1 cke0 0 0 r/w r/w clock enable 0 and 1 selects the clock source. asynchronous mode: 00: internal baud rate generator 01: internal baud rate generator outputs a clock of the same frequency as the bit rate from the sck3 pin. 10: external clock inputs a clock with a frequency 16 times the bit rate from the sck3 pin. 11:reserved clocked synchronous mode: 00: internal clock (sck3 pin functions as clock output) 01: reserved 10: external clock (sck3 pin functions as clock input) 11: reserved
section 14 serial communication interface 3 (sci3) rev. 6.00 mar. 24, 2006 page 203 of 412 rej09b0142-0600 14.3.7 serial status register (ssr) ssr is a register containing status flags of the sci3 and multiprocessor bits for transfer. 1 cannot be written to flags tdre, rdrf, oer, per, and fer; they can only be cleared. bit bit name initial value r/w description 7 tdre 1 r/w transmit data register empty displays whether tdr contains transmit data. [setting conditions] ? when the te bit in scr3 is 0 ? when data is transferred from tdr to tsr [clearing conditions] ? when 0 is written to tdre after reading tdre = 1 ? when the transmit data is written to tdr 6 rdrf 0 r/w receive data register full indicates that the received data is stored in rdr. [setting condition] when serial reception ends normally and receive data is transferred from rsr to rdr [clearing conditions] ? when 0 is written to rdrf after reading rdrf = 1 ? when data is read from rdr 5 oer 0 r/w overrun error [setting condition] when an overrun error occurs in reception [clearing condition] when 0 is written to oer after reading oer = 1 4 fer 0 r/w framing error [setting condition] when a framing error occurs in reception [clearing condition] when 0 is written to fer after reading fer = 1
section 14 serial communication interface 3 (sci3) rev. 6.00 mar. 24, 2006 page 204 of 412 rej09b0142-0600 bit bit name initial value r/w description 3 per 0 r/w parity error [setting condition] when a parity error is generated during reception [clearing condition] when 0 is written to per after reading per = 1 2 tend 1 r transmit end [setting conditions] ? when the te bit in scr3 is 0 ? when tdre = 1 at transmission of the last bit of a 1-byte serial transmit character [clearing conditions] ? when 0 is written to tend after reading tend = 1 ? when the transmit data is written to tdr 1 mpbr 0 r multiprocessor bit receive mpbr stores the multiprocessor bit in the receive character data. when the re bit in scr3 is cleared to 0, its previous state is retained. 0 mpbt 0 r/w multiprocessor bit transfer mpbt stores the multiprocessor bit to be added to the transmit character data.
section 14 serial communication interface 3 (sci3) rev. 6.00 mar. 24, 2006 page 205 of 412 rej09b0142-0600 14.3.8 bit rate register (brr) brr is an 8-bit register that adjusts the bit rate. the initial value of brr is h'ff. table 14.2 shows the relationship between the n setting in brr and the n setting in bits cks1 and cks0 of smr in asynchronous mode. table 14.3 show s the maximum bit rate for each frequency in asynchronous mode. the values shown in both ta bles 14.2 and 14.3 are values in active (high- speed) mode. table 14.4 shows the relationship between the n setting in brr and the n setting in bits cks1 and cks0 in smr in clocked synchronous mode. the values shown in table 14.4 are values in active (high-speed) mode. the n setting in brr and error for other operating frequencies and bit rates can be obtained by the following formulas: [asynchronous mode] n = 64 2 2n?1 b 10 6 ? 1 error (%) = ? 1 100 ? ? ? ? ? ? 10 6 (n + 1) b 64 2 2n?1 [clocked synchronous mode] n = 8 2 2n?1 b 10 6 ? 1 [legend] b: bit rate (bit/s) n: brr setting for baud rate generator (0 n 255) : operating frequency (mhz) n: cks1 and cks0 setting for smr (0 n 3)
section 14 serial communication interface 3 (sci3) rev. 6.00 mar. 24, 2006 page 206 of 412 rej09b0142-0600 table 14.2 examples of brr settings for various bit rates (asynchronous mode) (1) operating frequency (mhz) 2 2.097152 2.4576 3 bit rate (bits/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 1 141 0.03 1 148 ?0.04 1 174 ?0.26 1 212 0.03 150 1 103 0.16 1 108 0.21 1 127 0.00 1 155 0.16 300 0 207 0.16 0 217 0.21 0 255 0.00 1 77 0.16 600 0 103 0.16 0 108 0.21 0 127 0.00 0 155 0.16 1200 0 51 0.16 0 54 ?0.70 0 63 0.00 0 77 0.16 2400 0 25 0.16 0 26 1.14 0 31 0.00 0 38 0.16 4800 0 12 0.16 0 13 ?2.48 0 15 0.00 0 19 ?2.34 9600 0 6 ?6.99 0 6 ?2.48 0 7 0.00 0 9 ?2.34 19200 0 2 8.51 0 2 13.78 0 3 0.00 0 4 ?2.34 31250 0 1 0.00 0 1 4.86 0 1 22.88 0 2 0.00 38400 0 1 ?18.62 0 1 ?14.67 0 1 0.00 ? ? ? [legend] ? : a setting is available but error occurs operating frequency (mhz) 3.6864 4 4.9152 5 bit rate (bits/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 64 0.70 2 70 0.03 2 86 0.31 2 88 ?0.25 150 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16 300 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16 600 0 191 0.00 0 207 0.16 0 255 0.00 1 64 0.16 1200 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16 2400 0 47 0.00 0 51 0.16 0 63 0.00 0 64 0.16 4800 0 23 0.00 0 25 0.16 0 31 0.00 0 32 ?1.36 9600 0 11 0.00 0 12 0.16 0 15 0.00 0 15 1.73 19200 0 5 0.00 0 6 ?6.99 0 7 0.00 0 7 1.73 31250 ? ? ? 0 3 0.00 0 4 ?1.70 0 4 0.00 38400 0 2 0.00 0 2 8.51 0 3 0.00 0 3 1.73
section 14 serial communication interface 3 (sci3) rev. 6.00 mar. 24, 2006 page 207 of 412 rej09b0142-0600 table 14.2 examples of brr settings for various bit rates (asynchronous mode) (2) operating frequency (mhz) 6 6.144 7.3728 8 bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 106 ?0.44 2 108 0.08 2 130 ?0.07 2 141 0.03 150 2 77 0.16 2 79 0.00 2 95 0.00 2 103 0.16 300 1 155 0.16 1 159 0.00 1 191 0.00 1 207 0.16 600 1 77 0.16 1 79 0.00 1 95 0.00 1 103 0.16 1200 0 155 0.16 0 159 0.00 0 191 0.00 0 207 0.16 2400 0 77 0.16 0 79 0.00 0 95 0.00 0 103 0.16 4800 0 38 0.16 0 39 0.00 0 47 0.00 0 51 0.16 9600 0 19 ?2.34 0 19 0.00 0 23 0.00 0 25 0.16 19200 0 9 ?2.34 0 9 0.00 0 11 0.00 0 12 0.16 31250 0 5 0.00 0 5 2.40 0 6 5.33 0 7 0.00 38400 0 4 ?2.34 0 4 0.00 0 5 0.00 0 6 -6.99 operating frequency (mhz) 9.8304 10 12 12.888 bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 174 ?0.26 2 177 ?0.25 2 212 0.03 2 217 0.08 150 2 127 0.00 2 129 0.16 2 155 0.16 2 159 0.00 300 1 255 0.00 2 64 0.16 2 77 0.16 2 79 0.00 600 1 127 0.00 1 129 0.16 1 155 0.16 1 159 0.00 1200 0 255 0.00 1 64 0.16 1 77 0.16 1 79 0.00 2400 0 127 0.00 0 129 0.16 0 155 0.16 0 159 0.00 4800 0 63 0.00 0 64 0.16 0 77 0.16 0 79 0.00 9600 0 31 0.00 0 32 ?1.36 0 38 0.16 0 39 0.00 19200 0 15 0.00 0 15 1.73 0 19 ?2.34 0 19 0.00 31250 0 9 ?1.70 0 9 0.00 0 11 0.00 0 11 2.40 38400 0 7 0.00 0 7 1.73 0 9 ?2.34 0 9 0.00
section 14 serial communication interface 3 (sci3) rev. 6.00 mar. 24, 2006 page 208 of 412 rej09b0142-0600 table 14.2 examples of brr settings for various bit rates (asynchronous mode) (3) operating frequency (mhz) 14 14.7456 16 bit rate (bit/s) n n error (%) n n error (%) n n error (%) 110 2 248 ?0.17 3 64 0.70 3 70 0.03 150 2 181 0.16 2 191 0.00 2 207 0.16 300 2 90 0.16 2 95 0.00 2 103 0.16 600 1 181 0.16 1 191 0.00 1 207 0.16 1200 1 90 0.16 1 95 0.00 1 103 0.16 2400 0 181 0.16 0 191 0.00 0 207 0.16 4800 0 90 0.16 0 95 0.00 0 103 0.16 9600 0 45 ?0.93 0 47 0.00 0 51 0.16 19200 0 22 ?0.93 0 23 0.00 0 25 0.16 31250 0 13 0.00 0 14 ?1.70 0 15 0.00 38400 ? ? ? 0 11 0.00 0 12 0.16 [legend] ?: a setting is available but error occurs. table 14.3 maximum bit rate for ea ch frequency (asynchronous mode) (mhz) maximum bit rate (bit/s) n n (mhz) maximum bit rate (bit/s) n n 2 62500 0 0 7.3728 230400 0 0 2.097152 65536 0 0 8 250000 0 0 2.4576 76800 0 0 9.8304 307200 0 0 3 93750 0 0 10 312500 0 0 3.6864 115200 0 0 12 375000 0 0 4 125000 0 0 12.288 384000 0 0 4.9152 153600 0 0 14 437500 0 0 5 156250 0 0 14.7456 460800 0 0 6 187500 0 0 16 500000 0 0 6.144 192000 0 0
section 14 serial communication interface 3 (sci3) rev. 6.00 mar. 24, 2006 page 209 of 412 rej09b0142-0600 table 14.4 brr settings for various bi t rates (clocked synchronous mode) operating frequency (mhz) 2 4 8 10 16 bit rate (bit/s) n n n n n n n n n n 110 3 70 ? ? ? ? ? ? 250 2 124 2 249 3 124 ? ? 3 249 500 1 249 2 124 2 249 ? ? 3 124 1k 1 124 1 249 2 124 ? ? 2 249 2.5k 0 199 1 99 1 199 1 249 2 99 5k 0 99 0 199 1 99 1 124 1 199 10k 0 49 0 99 0 199 0 249 1 99 25k 0 19 0 39 0 79 0 99 0 159 50k 0 9 0 19 0 39 0 49 0 79 100k 0 4 0 9 0 19 0 24 0 39 250k 0 1 0 3 0 7 0 9 0 15 500k 0 0 * 0 1 0 3 0 4 0 7 1m 0 0 * 0 1 ? ? 0 3 2m 0 0 * ? ? 0 1 2.5m 0 0 * ? ? 4m 0 0 * [legend] blank: no setting is available. ?: a setting is available but error occurs. * : continuous transfer is not possible.
section 14 serial communication interface 3 (sci3) rev. 6.00 mar. 24, 2006 page 210 of 412 rej09b0142-0600 14.4 operation in asynchronous mode figure 14.2 shows the general format for asynchronous serial communication. one frame consists of a start bit (low level), followed by data (in lsb-first order), a parity bit (high or low level), and finally stop bits (high level). in side the sci3, the transmitter an d receiver are independent units, enabling full duplex. both the tran smitter and the receiver also have a double-buffered structure, so data can be read or written during transmission or reception, enabling continuous data transfer. lsb start bit msb mark state stop bit transmit/receive data 1 serial data parity bit 1 bit 1 or 2 bits 7 or 8 bits 1 bit, or none one unit of transfer data (character or frame) figure 14.2 data format in asynchronous communication 14.4.1 clock either an internal clock generated by the on-chip baud rate generator or an external clock input at the sck3 pin can be selected as the sci3?s serial clock source, according to the setting of the com bit in smr and the cke0 and cke1 bits in scr3. when an external clock is input at the sck3 pin, the clock frequency should be 16 times the bit rate used. when the sci3 is operated on an internal clock, the clock can be output from the sck3 pin. the frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 14.3. 0 1 character (frame) d0 d1 d2 d3 d4 d5 d6 d7 0/1 11 clock serial data figure 14.3 relationship between output clock and transfer data phase (asynchronous mode) (example with 8-bit data, parity, two stop bits)
section 14 serial communication interface 3 (sci3) rev. 6.00 mar. 24, 2006 page 211 of 412 rej09b0142-0600 14.4.2 sci3 initialization follow the flowchart as shown in figure 14.4 to initialize the sci3. when the te bit is cleared to 0, the tdre flag is set to 1. note that clearing the re bit to 0 does not initialize the contents of the rdrf, per, fer, and oer flags, or the contents of rdr. when the external clock is used in asynchronous mode, the clock must be supplied even during initialization. wait start initialization set data transfer format in smr [1] set cke1 and cke0 bits in scr3 no yes set value in brr clear te and re bits in scr3 to 0 [2] [3] set te and re bits in scr3 to 1, and set rie, tie, teie, and mpie bits. for transmit (te=1), also set the txd bit in pmr1. [4] 1-bit interval elapsed? [1] set the clock selection in scr3. be sure to clear bits rie, tie, teie, and mpie, and bits te and re, to 0. when the clock output is selected in asynchronous mode, clock is output immediately after cke1 and cke0 settings are made. when the clock output is selected at reception in clocked synchronous mode, clock is output immediately after cke1, cke0, and re are set to 1. [2] set the data transfer format in smr. [3] write a value corresponding to the bit rate to brr. not necessary if an external clock is used. [4] wait at least one bit interval, then set the te bit or re bit in scr3 to 1. re settings enable the rxd pin to be used. for transmission, set the txd bit in pmr1 to 1 to enable the txd output pin to be used. also set the rie, tie, teie, and mpie bits, depending on whether interrupts are required. in asynchronous mode, the bits are marked at transmission and idled at reception to wait for the start bit. figure 14.4 sample sci3 initialization flowchart
section 14 serial communication interface 3 (sci3) rev. 6.00 mar. 24, 2006 page 212 of 412 rej09b0142-0600 14.4.3 data transmission figure 14.5 shows an example of operation for transmission in asynchronous mode. in transmission, the sci3 operates as described below. 1. the sci3 monitors the tdre flag in ssr. if the flag is cleared to 0, th e sci3 recognizes that data has been written to tdr, and transfers the data from tdr to tsr. 2. after transferring data from tdr to tsr, the sci3 sets the tdre flag to 1 and starts transmission. if the tie bit is set to 1 at th is time, a txi interrupt request is generated. continuous transmission is possible because the txi interrupt routine writes next transmit data to tdr before transmission of the current transmit data has been completed. 3. the sci3 checks the tdre flag at the timing for sending the stop bit. 4. if the tdre flag is 0, the data is transferred from tdr to tsr, the stop bit is sent, and then serial transmission of the next frame is started. 5. if the tdre flag is 1, the tend flag in ssr is set to 1, the stop bit is sent, and then the ?mark state? is entered, in which 1 is output. if the tei e bit in scr3 is set to 1 at this time, a tei interrupt request is generated. 6. figure 14.6 shows a sample flowchart for transmission in asynchronous mode. 1 frame start bit start bit transmit data transmit data parity bit stop bit parity bit stop bit mark state 1 frame 0 1d0d1d70/11 11 0d0d1 d70/1 serial data tdre tend lsi operation txi interrupt request generated tdre flag cleared to 0 user processing data written to tdr txi interrupt request generated tei interrupt request generated figure 14.5 example sci3 operation in transmission in asynchronous mode (8-bit data, parity, one stop bit)
section 14 serial communication interface 3 (sci3) rev. 6.00 mar. 24, 2006 page 213 of 412 rej09b0142-0600 no yes start transmission read tdre flag in ssr [1] write transmit data to tdr yes no no yes read tend flag in ssr [2] no yes [3] clear pdr to 0 and set pcr to 1 clear te bit in scr3 to 0 tdre = 1 all data transmitted? tend = 1 break output? [1] read ssr and check that the tdre flag is set to 1, then write transmit data to tdr. when data is written to tdr, the tdre flag is automaticaly cleared to 0. [2] to continue serial transmission, read 1 from the tdre flag to confirm that writing is possible, then write data to tdr. when data is written to tdr, the tdre flag is automaticaly cleared to 0. [3] to output a break in serial transmission, after setting pcr to 1 and pdr to 0, clear txd in pmr1 to 0, then clear the te bit in scr3 to 0. figure 14.6 sample serial transmission flowchart (asynchronous mode)
section 14 serial communication interface 3 (sci3) rev. 6.00 mar. 24, 2006 page 214 of 412 rej09b0142-0600 14.4.4 serial data reception figure 14.7 shows an example of operation for reception in asynchronous mode. in serial reception, the sci operates as described below. 1. the sci3 monitors the communication line. if a start bit is detected, the sci3 performs internal synchronization, receives data in rsr, and checks the parity bit and stop bit. 2. if an overrun error occurs (when reception of the next data is completed while the rdrf flag is still set to 1), the oer bit in ssr is set to 1. if the rie bit in scr3 is set to 1 at this time, an eri interrupt request is generated. recei ve data is not transferred to rdr. 3. if a parity error is detected, the per bit in ss r is set to 1 and receive data is transferred to rdr. if the rie bit in scr3 is set to 1 at this time, an eri interrupt request is generated. 4. if a framing error is detected (when the stop bit is 0), the fer bit in ssr is set to 1 and receive data is transferred to rdr. if the rie bit in scr3 is set to 1 at this time, an eri interrupt request is generated. 5. if reception is completed succe ssfully, the rdrf bit in ssr is set to 1, and receive data is transferred to rdr. if the rie bit in scr3 is set to 1 at this time, an rxi interrupt request is generated. continuous reception is possible because the rxi inte rrupt routine r eads the receive data transferred to rdr before reception of the next receive data has been completed. 1 frame start bit start bit receive data receive data parity bit stop bit parity bit stop bit mark state (idle state) 1 frame 0 1d0d1d70/11 01 0d0d1 d70/1 serial data rdrf fer lsi operation user processing rdrf cleared to 0 rdr data read framing error processing rxi request 0 stop bit detected eri request in response to framing error figure 14.7 example sci3 operation in reception in asynchronous mode (8-bit data, parity, one stop bit)
section 14 serial communication interface 3 (sci3) rev. 6.00 mar. 24, 2006 page 215 of 412 rej09b0142-0600 table 14.5 shows the states of th e ssr status flags and receive da ta handling when a receive error is detected. if a receive error is detected, the rdrf flag retains its state before receiving data. reception cannot be resumed while a receive error fl ag is set to 1. accordingly, clear the oer, fer, per, and rdrf bits to 0 before resuming reception. figure 14.8 shows a sample flowchart for serial data reception. table 14.5 ssr status flag s and receive data handling ssr status flag rdrf * oer fer per receive data receive error type 1 1 0 0 lost overrun error 0 0 1 0 transferred to rdr framing error 0 0 0 1 transferred to rdr parity error 1 1 1 0 lost overrun error + framing error 1 1 0 1 lost overrun error + parity error 0 0 1 1 transferred to rdr framing error + parity error 1 1 1 1 lost overrun error + framing error + parity error note: * the rdrf flag retains the stat e it had before data reception.
section 14 serial communication interface 3 (sci3) rev. 6.00 mar. 24, 2006 page 216 of 412 rej09b0142-0600 yes no start reception [1] no yes read rdrf flag in ssr [2] [3] clear re bit in scr3 to 0 read oer, per, and fer flags in ssr error processing (continued on next page) [4] read receive data in rdr yes no oer+per+fer = 1 rdrf = 1 all data received? [1] read the oer, per, and fer flags in ssr to identify the error. if a receive error occurs, performs the appropriate error processing. [2] read ssr and check that rdrf = 1, then read the receive data in rdr. the rdrf flag is cleared automatically. [3] to continue serial reception, before the stop bit for the current frame is received, read the rdrf flag and read rdr. the rdrf flag is cleared automatically. [4] if a receive error occurs, read the oer, per, and fer flags in ssr to identify the error. after performing the appropriate error processing, ensure that the oer, per, and fer flags are all cleared to 0. reception cannot be resumed if any of these flags are set to 1. in the case of a framing error, a break can be detected by reading the value of the input port corresponding to the rxd pin. (a) figure 14.8 sample seri al data reception flowchar t (asynchronous mode) (1)
section 14 serial communication interface 3 (sci3) rev. 6.00 mar. 24, 2006 page 217 of 412 rej09b0142-0600 (a) error processing parity error processing yes no clear oer, per, and fer flags in ssr to 0 no yes no yes framing error processing no yes overrun error processing oer = 1 fer = 1 break? per = 1 [4] figure 14.8 sample serial reception data flowchart (2)
section 14 serial communication interface 3 (sci3) rev. 6.00 mar. 24, 2006 page 218 of 412 rej09b0142-0600 14.5 operation in clocked synchronous mode figure 14.9 shows the general format for clocked synchronous communication. in clocked synchronous mode, data is transmitted or received synchronous with clock pulses. a single character in the transmit data co nsists of the 8-bit data starti ng from the lsb. in clocked synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. in clocked synchronous mode, the sc i3 receives data in synchronous with the rising edge of the serial clock. after 8-bit data is output, the transmission line holds the msb state. in clocked synchronous mode, no parity or multiprocessor bit is added. inside the sci3, the transmitter and receiver are independent units, enabling full-duplex communication through the use of a common cloc k. both the transmitter and th e receiver also have a double- buffered structure, so data can be read or wr itten during transmission or reception, enabling continuous data transfer. don't care don't care one unit of transfer data (character or frame) 8-bit bit 0 serial data synchronization clock bit 1 bit 3 bit 4 bit 5 lsb msb bit 2 bit 6 bit 7 * * note: * high except in continuous transfer figure 14.9 data format in clocked synchronous communication 14.5.1 clock either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the sck3 pin can be selected, according to the setting of the com bit in smr and cke0 and cke1 bits in scr3. when the sci3 is operated on an internal clock, the serial clock is output from the sck3 pin. eight serial clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. 14.5.2 sci3 initialization before transmitting and receiving data, the sci3 sh ould be initialized as described in a sample flowchart in figure 14.4.
section 14 serial communication interface 3 (sci3) rev. 6.00 mar. 24, 2006 page 219 of 412 rej09b0142-0600 14.5.3 serial data transmission figure 14.10 shows an example of sci3 operation for transmission in clocked synchronous mode. in serial transmission, the sci3 operates as described below. 1. the sci3 monitors the tdre flag in ssr, and if the flag is 0, the sci re cognizes that data has been written to tdr, and transf ers the data from tdr to tsr. 2. the sci3 sets the tdre flag to 1 and starts tr ansmission. if the tie bit in scr3 is set to 1 at this time, a transmit data empty interrupt (txi) is generated. 3. 8-bit data is sent from the txd pin synchronized with the output clock when output clock mode has been specified, and synchronized with the input clock when use of an external clock has been specified. serial data is transmitted sequentially from the lsb (bit 0), from the txd pin. 4. the sci checks the tdre flag at the timing for sending the msb (bit 7). 5. if the tdre flag is cleared to 0, data is tr ansferred from tdr to tsr, and serial transmission of the next frame is started. 6. if the tdre flag is set to 1, the tend flag in ssr is set to 1, and the tdre flag maintains the output state of the last bit. if the teie bit in scr3 is set to 1 at this time, a tei interrupt request is generated. 7. the sck3 pin is fixed high. figure 14.11 shows a sample flowchart for serial data transmission. even if the tdre flag is cleared to 0, transmission will not start while a r eceive error flag (oer, fer, or per) is set to 1. make sure that the receive error flags are cleared to 0 before starting transmission. serial clock serial data bit 1 bit 0 bit 7 bit 0 1 frame 1 frame bit 1 bit 6 bit 7 tdre tend lsi operation user processing txi interrupt request generated data written to tdr tdre flag cleared to 0 txi interrupt request generated tei interrupt request generated figure 14.10 example of sci3 operation in transmission in clocked synchronous mode
section 14 serial communication interface 3 (sci3) rev. 6.00 mar. 24, 2006 page 220 of 412 rej09b0142-0600 no yes start transmission read tdre flag in ssr [1] write transmit data to tdr no yes no yes read tend flag in ssr [2] clear te bit in scr3 to 0 tdre = 1 all data transmitted? tend = 1 [1] read ssr and check that the tdre flag is set to 1, then write transmit data to tdr. when data is written to tdr, the tdre flag is automatically cleared to 0 and clocks are output to start the data transmission. [2] to continue serial transmission, be sure to read 1 from the tdre flag to confirm that writing is possible, then write data to tdr. when data is written to tdr, the tdre figure 14.11 sample serial transmission flowchart (clocked synchronous mode)
section 14 serial communication interface 3 (sci3) rev. 6.00 mar. 24, 2006 page 221 of 412 rej09b0142-0600 14.5.4 serial data reception (clocked synchronous mode) figure 14.12 shows an example of sci3 operation for reception in clocked synchronous mode. in serial reception, the sci3 operates as described below. 1. the sci3 performs internal initialization synchronous with a synchronous clock input or output, starts receiving data. 2. the sci3 stores the received data in rsr. 3. if an overrun error occurs (when reception of the next data is completed while the rdrf flag in ssr is still set to 1), the oer bit in ssr is set to 1. if the rie bit in scr3 is set to 1 at this time, an eri interrupt request is generated, re ceive data is not transferred to rdr, and the rdrf flag remains to be set to 1. 4. if reception is comple ted successfully, the rdrf bit in ssr is set to 1, and receive data is transferred to rdr. if the rie bit in scr3 is set to 1 at this time, an rxi interrupt request is generated. serial clock serial data 1 frame 1 frame bit 0 bit 7 bit 7 bit 0 bit 1 bit 6 bit 7 rdrf oer lsi operation user processing rxi interrupt request generated rdr data read rdrf flag cleared to 0 rxi interrupt request generated eri interrupt request generated by overrun error overrun error processing rdr data has not been read (rdrf = 1) figure 14.12 example of sci3 reception operation in clocked synchronous mode
section 14 serial communication interface 3 (sci3) rev. 6.00 mar. 24, 2006 page 222 of 412 rej09b0142-0600 reception cannot be resumed while a receive error flag is set to 1. accordingly, clear the oer, fer, per, and rdrf bits to 0 before resuming r eception. figure 14.13 shows a sample flowchart for serial data reception. yes no start reception [1] [4] no yes read rdrf flag in ssr [2] [3] clear re bit in scr3 to 0 error processing (continued below) read receive data in rdr yes no oer = 1 rdrf = 1 all data received? read oer flag in ssr error processing overrun error processing clear oer flag in ssr to 0 [4] [1] read the oer flag in ssr to determine if there is an error. if an overrun error has occurred, execute overrun error processing. [2] read ssr and check that the rdrf flag is set to 1, then read the receive data in rdr. when data is read from rdr, the rdrf flag is automatically cleared to 0. [3] to continue serial reception, before the msb (bit 7) of the current frame is received, reading the rdrf flag and reading rdr should be finished. when data is read from rdr, the rdrf flag is automatically cleared to 0. [4] if an overrun error occurs, read the oer flag in ssr, and after performing the appropriate error processing, clear the oer flag to 0. reception cannot be figure 14.13 sample serial reception flowchart (clocked synchronous mode)
section 14 serial communication interface 3 (sci3) rev. 6.00 mar. 24, 2006 page 223 of 412 rej09b0142-0600 14.5.5 simultaneous serial data transmission and reception figure 14.14 shows a samp le flowchart for simulta neous serial transmit and receive operations. the following procedure should be used for simultaneous serial data transmit and receive operations. to switch from transmit mode to si multaneous transmit and receive mode, after checking that the sci3 has finished transmission and the tdre and tend flags are set to 1, clear te to 0. then simultaneously set te and re to 1 with a single instruction. to switch from receive mode to simultaneous transmit and receive mode , after checking that the sci3 has finished reception, clear re to 0. then after checking th at the rdrf and receive error flags (oer, fer, and per) are cleared to 0, simultaneously se t te and re to 1 with a single instruction. yes no start transmission/reception [3] error processing [4] read receive data in rdr yes no oer = 1 all data received? [1] read tdre flag in ssr no yes tdre = 1 write transmit data to tdr no yes rdrf = 1 read oer flag in ssr [2] read rdrf flag in ssr clear te and re bits in scr to 0 [1] read ssr and check that the tdre flag is set to 1, then write transmit data to tdr. when data is written to tdr, the tdre flag is automatically cleared to 0. [2] read ssr and check that the rdrf flag is set to 1, then read the receive data in rdr. when data is read from rdr, the rdrf flag is automatically cleared to 0. [3] to continue serial transmission/ reception, before the msb (bit 7) of the current frame is received, finish reading the rdrf flag, reading rdr. also, before the msb (bit 7) of the current frame is transmitted, read 1 from the tdre flag to confirm that writing is possible. then write data to tdr. when data is written to tdr, the tdre flag is automatically cleared to 0. when data is read from rdr, the rdrf flag is automatically cleared to 0. [4] if an overrun error occurs, read the oer flag in ssr, and after performing the appropriate error processing, clear the oer flag to 0. transmission/reception cannot be resumed if the oer flag is set to 1. for overrun error processing, see figure 14.13. figure 14.14 sample flowchart of simultaneo us serial transmit and receive operations (clocked synchronous mode)
section 14 serial communication interface 3 (sci3) rev. 6.00 mar. 24, 2006 page 224 of 412 rej09b0142-0600 14.6 multiprocessor communication function use of the multiprocessor communication function enables data transfer between a number of processors sharing communication lines by asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. when multiprocessor commun ication is performed, each receiving st ation is addressed by a unique id code. the serial communication cy cle consists of two component cy cles; an id transmission cycle that specifies the receiving station, and a data transmission cycl e. the multiprocessor bit is used to differentiate between the id tr ansmission cycle and the data transmission cycle. if the multiprocessor bit is 1, the cycle is an id transm ission cycle; if the mul tiprocessor bit is 0, the cycle is a data transmission cycle. figure 14.15 shows an example of inter-processor communication using the multiprocessor format. the transmitting station first sends the id code of the receiving station with wh ich it wants to perform serial co mmunication as data with a 1 multiprocessor bit added. it then sends transmit data as data with a 0 multiprocessor bit added. when data with a 1 multiprocessor bit is received, the r eceiving station compares that data with its own id. the station whose id matc hes then receives the data sent next. stations whose ids do not match continue to skip data until data w ith a 1 multiprocessor bi t is again received. the sci3 uses the mpie bit in scr3 to implement this function. when the mpie bit is set to 1, transfer of receive data from rsr to rdr, error flag detection, and setting the ssr status flags, rdrf, fer, and oer to 1, are inhibited until da ta with a 1 multiprocesso r bit is received. on reception of a receive character w ith a 1 multiprocessor bit, the mpbr bit in ssr is set to 1 and the mpie bit is automatically cleared, thus normal reception is resumed. if the rie bit in scr3 is set to 1 at this time, an rxi interrupt is generated. when the multiprocessor format is selected, the parity bit setting is rendered invalid. all other bit settings are the same as those in normal asynchronous mode. the clock used for multiprocessor communication is the same as that in normal asynchronous mode.
section 14 serial communication interface 3 (sci3) rev. 6.00 mar. 24, 2006 page 225 of 412 rej09b0142-0600 transmitting station receiving station a receiving station b receiving station c receiving station d (id = 01) (id = 02) (id = 03) (id = 04) serial transmission line serial data id transmission cycle = receiving station specification data transmission cycle = data transmission to receiving station specified by id (mpb = 1) (mpb = 0) h'01 h'aa [legend] mpb: multiprocessor bit figure 14.15 example of communica tion using multip rocessor format (transmission of data h'aa to receiving station a)
section 14 serial communication interface 3 (sci3) rev. 6.00 mar. 24, 2006 page 226 of 412 rej09b0142-0600 14.6.1 multiprocessor seri al data transmission figure 14.16 shows a sample flowchart for multip rocessor serial data transmission. for an id transmission cycle, set the mpbt bit in ssr to 1 before transmission. for a data transmission cycle, clear the mpbt b it in ssr to 0 before transmission. all other sci3 operations are the same as those in asynchronous mode. no yes start transmission read tdre flag in ssr [1] set mpbt bit in ssr yes no no yes read tend flag in ssr [2] no yes [3] clear pdr to 0 and set pcr to 1 clear te bit in scr3 to 0 tdre = 1 all data transmitted? tend = 1 break output? write transmit data to tdr [1] read ssr and check that the tdre flag is set to 1, set the mpbt bit in ssr to 0 or 1, then write transmit data to tdr. when data is written to tdr, the tdre flag is automatically cleared to 0. [2] to continue serial transmission, be sure to read 1 from the tdre flag to confirm that writing is possible, then write data to tdr. when data is written to tdr, the tdre flag is automatically cleared to 0. [3] to output a break in serial transmission, set the port pcr to 1, clear pdr to 0, then clear the te bit in scr3 to 0. figure 14.16 sample multiprocessor serial tr ansmission flowchart
section 14 serial communication interface 3 (sci3) rev. 6.00 mar. 24, 2006 page 227 of 412 rej09b0142-0600 14.6.2 multiprocessor s erial data reception figure 14.17 shows a sample flowchart for multiproces sor serial data reception. if the mpie bit in scr3 is set to 1, data is skipped until data with a 1 multiprocessor bit is received. on receiving data with a 1 multiprocessor bit, the receive data is transferred to rdr. an rxi interrupt request is generated at this time. all other sci3 operations are the same as in asynchronous mode. figure 14.18 shows an example of sci3 operatio n for multiprocessor format reception. yes no start reception no yes [4] clear re bit in scr3 to 0 error processing (continued on next page) [5] yes no fer+oer = 1 rdrf = 1 all data received? set mpie bit in scr3 to 1 [1] [2] read oer and fer flags in ssr read rdrf flag in ssr [3] read receive data in rdr no yes [a] this station's id? read oer and fer flags in ssr yes no read rdrf flag in ssr no yes fer+oer = 1 read receive data in rdr rdrf = 1 [1] set the mpie bit in scr3 to 1. [2] read oer and fer in ssr to check for errors. receive error processing is performed in cases where a receive error occurs. [3] read ssr and check that the rdrf flag is set to 1, then read the receive data in rdr and compare it with this station?s id. if the data is not this station?s id, set the mpie bit to 1 again. when data is read from rdr, the rdrf flag is automatically cleared to 0. [4] read ssr and check that the rdrf flag is set to 1, then read the data in rdr. [5] if a receive error occurs, read the oer and fer flags in ssr to identify the error. after performing the appropriate error processing, ensure that the oer and fer flags are all cleared to 0. reception cannot be resumed if either of these flags is set to 1. in the case of a framing error, a break can be detected by reading the rxd pin value. figure 14.17 sample multiprocessor serial reception flowchart (1)
section 14 serial communication interface 3 (sci3) rev. 6.00 mar. 24, 2006 page 228 of 412 rej09b0142-0600 error processing yes no clear oer, and fer flags in ssr to 0 no yes no yes framing error processing overrun error processing oer = 1 fer = 1 break? [5] [a] figure 14.17 sample multiprocessor serial reception flowchart (2)
section 14 serial communication interface 3 (sci3) rev. 6.00 mar. 24, 2006 page 229 of 412 rej09b0142-0600 1 frame start bit start bit receive data (id1) receive data (data1) mpb mpb stop bit stop bit mark state (idle state) 1 frame 0 1d0d1d711 11 0d0d1 d7 id1 0 serial data mpie rdrf rdr value rdr value lsi operation rxi interrupt request mpie cleared to 0 user processing rdrf flag cleared to 0 rxi interrupt request is not generated, and rdr retains its state rdr data read when data is not this station's id, mpie is set to 1 again 1 frame start bit start bit receive data (id2) receive data (data2) mpb mpb stop bit stop bit mark state (idle state) 1 frame 0 1d0d1d711 11 0 (a) when data does not match this receiver's id (b) when data matches this receiver's id d0 d1 d7 id2 data2 id1 0 serial data mpie rdrf lsi operation rxi interrupt request mpie cleared to 0 user processing rdrf flag cleared to 0 rxi interrupt request rdrf flag cleared to 0 rdr data read when data is this station's id, reception is continued rdr data read mpie set to 1 again figure 14.18 example of sc i3 operation in reception using multipro cessor format (example with 8-bit data, multiprocessor bit, one stop bit)
section 14 serial communication interface 3 (sci3) rev. 6.00 mar. 24, 2006 page 230 of 412 rej09b0142-0600 14.7 interrupts the sci3 creates the following six interrupt requests: transmission end, transmit data empty, receive data full, and receive erro rs (overrun error, framing error, and parity error). table 14.6 shows the interrupt sources. table 14.6 sci3 interrupt requests interrupt requests abbreviation interrupt sources receive data full rxi setting rdrf in ssr transmit data empty txi setting tdre in ssr transmission end tei setting tend in ssr receive error eri setting oer, fer, and per in ssr the initial value of the tdre flag in ssr is 1. thus, when the tie bit in scr3 is set to 1 before transferring the transmit data to tdr, a txi interr upt request is generated even if the transmit data is not ready. the initial value of the tend flag in ssr is 1. thus, when the teie bit in scr3 is set to 1 before transferring the transmit data to tdr, a tei interrupt request is generated even if the transmit data has not been sent. it is possib le to make use of the most of these interrupt requests efficiently by transferring the transmit da ta to tdr in the interrupt routine. to prevent the generation of these interrupt requests (txi an d tei), set the enable bits (tie and teie) that correspond to these in terrupt requests to 1, after transf erring the transmit data to tdr. 14.8 usage notes 14.8.1 break detection and processing when framing error detection is performed, a break can be detected by reading the rxd pin value directly. in a break, the input from the rxd pin becomes all 0, setting the fer flag, and possibly the per flag. note that as the sci3 continues the receive operation after receiving a break, even if the fer flag is cleared to 0, it will be set to 1 again.
section 14 serial communication interface 3 (sci3) rev. 6.00 mar. 24, 2006 page 231 of 412 rej09b0142-0600 14.8.2 mark state and break sending when te is 0, the txd pin is used as an i/o port whose direction (input or output) and level are determined by pcr and pdr. this can be used to set the txd pin to mark state (high level) or send a break during serial data transmission. to maintain the communicat ion line at mark state until te is set to 1, set both pcr and pdr to 1. as te is cleared to 0 at this point, the txd pin becomes an i/o port, and 1 is output from the txd pin. to send a break during serial transmission, first set pcr to 1 and pdr to 0, and then clear te to 0. when te is cleared to 0, the transmitter is initialized regardless of the current transmission st ate, the txd pin becomes an i/o port, and 0 is output from the txd pin. 14.8.3 receive error flags and transmit op erations (clocked synchronous mode only) transmission cannot be started when a receive error flag (oer, per, or fer) is set to 1, even if the tdre flag is cleared to 0. be sure to cl ear the receive error flag s to 0 before starting transmission. note also that receive error flags cannot be cleared to 0 even if the re bit is cleared to 0. 14.8.4 receive data samplin g timing and reception marg in in asynchronous mode in asynchronous mode, the sci3 operates on a basic clock with a frequency of 16 times the transfer rate. in receptio n, the sci3 samples the falling edge of the start bit using the basic clock, and performs internal synchronization. receive data is latched internally at the rising edge of the 8th pulse of the basic clock as shown in figure 14.19. thus, the reception margin in asynchronous mode is given by formula (1) below. m = (0.5 ? ) ? ? (l ? 0.5) f 100(%) ? ? ? ? ? ? 1 2n d ? 0.5 n ... formula (1) where n: ratio of bit rate to clock (n = 16) d: clock duty (d = 0.5 to 1.0) l: frame length (l = 9 to 12) f: absolute value of clock rate deviation
section 14 serial communication interface 3 (sci3) rev. 6.00 mar. 24, 2006 page 232 of 412 rej09b0142-0600 assuming values of f (absolute value of clock rate deviation) = 0 and d (clock duty) = 0.5 in formula (1), the reception margin can be given by the formula. m = {0.5 ? 1/(2 16)} 100 [%] = 46.875% however, this is only the computed value, and a margin of 20% to 30% should be allowed for in system design. internal basic clock 16 clocks 8 clocks receive data (rxd) synchronization sampling timing start bit d0 d1 data sampling timing 15 0 7 15 0 0 7 figure 14.19 receive data sampling timing in asynchronous mode
section 15 i 2 c bus interface (iic) rev. 6.00 mar. 24, 2006 page 233 of 412 rej09b0142-0600 section 15 i 2 c bus interface (iic) the i 2 c bus interface conforms to and pr ovides a subset of the philips i 2 c bus (inter-ic bus) interface functions. the register co nfiguration that controls the i 2 c bus differs partly from the philips configuration, however. 15.1 features ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
section 15 i 2 c bus interface (iic) rev. 6.00 mar. 24, 2006 page 234 of 412 rej09b0142-0600 figure 15.1 shows a block diagram of the i 2 c bus interface. figure 15.2 shows an example of i/o pin connections to external circuits. the i/o pins are nmos open drains. set the upper limit of vo ltage applied to th e power supply (v cc ) voltage range + 0.3 v, i.e. 5.8 v. ps noise canceler noise canceler clock control bus state decision circuit arbitration decision circuit output data control circuit address comparator sar, sarx interrupt generator icdrs icdrr icdrt icsr icmr iccr internal data bus interrupt request scl sda [legend] iccr: icmr: icsr: icdr: sar: sarx: ps: i 2 c bus control register i 2 c bus mode register i 2 c bus status register i 2 c bus data register slave address register slave address register x prescaler figure 15.1 block diagram of i 2 c bus interface
section 15 i 2 c bus interface (iic) rev. 6.00 mar. 24, 2006 page 235 of 412 rej09b0142-0600 scl in scl out sda in sda out (slave 1) scl sda scl in scl out sda in sda out (slave 2) scl sda scl in scl out sda in sda out (master) this lsi scl sda v dd v cc scl sda figure 15.2 i 2 c bus interface connections (example: this lsi as master) 15.2 input/output pins table 15.1 summarizes the input/output pins used by the i 2 c bus interface. table 15.1 i 2 c bus interface pins name abbreviation i/o function serial clock scl i/o iic se rial clock input/output serial data sda i/o iic serial data input/output
section 15 i 2 c bus interface (iic) rev. 6.00 mar. 24, 2006 page 236 of 412 rej09b0142-0600 15.3 register descriptions the i 2 c bus interface has the followin g registers. icdr, sarx, icmr, and sar are allocated to one address, and registers that can be accessed de pend on the ice bit in iccr. when ice = 0. sar and sarx can be accessed. when ice = 1, icmr and icdr can be accessed. ? ? ? ? ? ? ? 15.3.1 i 2 c bus data register (icdr) icdr is an 8-bit readable/writable register that is used as a transmit data register when transmitting and a receive data register when recei ving. icdr is divided internally into a shift register (icdrs), receive buffer (icdrr), and tr ansmit buffer (icdrt). data transfers among the three registers are performed auto matically in coordination with changes in the bus state, and affect the status of internal flags such as tdre and rdrf. when tdre is 1 and the transmit buffer is empty, tdre shows that the next transmit data can be written from the cpu. when rdrf is 1, it shows that th e valid receive data is stored in the receive buffer. if i 2 c is in transmit mode and the next data is in icdrt (the tdre flag is 0) following transmission/reception of one frame of data using icdrs, data is transferred automatically from icdrt to icdrs. if i 2 c is in receive mode and no previous data remains in icdrr (the rdrf flag is 0) following transmission/ reception of one frame of data using icdrs, data is transferred automatically from icdrs to icdrr. if the number of bits in a frame, excluding the ackno wledge bit, is less than 8, transmit data and receive data are stored differently. transmit data should be written justified toward the msb side when mls = 0, and toward the lsb side when mls = 1. receive data bits read from the lsb side should be treated as valid when mls = 0, and bits read from the msb side when mls = 1. icdr can be written and read only when the ice bit is set to 1 in iccr. the value of icdr is undefined after a reset.
section 15 i 2 c bus interface (iic) rev. 6.00 mar. 24, 2006 page 237 of 412 rej09b0142-0600 the tdre and rdrf flags are set and cleared under the conditions shown below. setting the tdre and rdrf flags affects the status of the interrupt flags. bit bit name initial value r/w description ? tdre ? ? transmit data register empty [setting conditions] ? in transmit mode, when a start condition is detected in the bus line state after a start condition is issued in master mode with the i 2 c bus format or serial format selected ? when transmit mode (trs = 1) is set without a format ? when data is transferred from icdrt to icdrs ? when a switch is made from receive mode to transmit mode after detection of a start condition [clearing conditions] ? when transmit data is written in icdr in transmit mode ? when a stop condition is detected in the bus line state after a stop condition is issued with the i2c bus format or serial format selected ? when a stop condition is detected with the i2c bus format selected ? in receive mode ? rdrf ? ? receive data register full [setting condition] when data is transferred from icdrs to icdrr [clearing condition] when icdr (icdrr) receive data is read in receive mode
section 15 i 2 c bus interface (iic) rev. 6.00 mar. 24, 2006 page 238 of 412 rej09b0142-0600 15.3.2 slave address register (sar) sar selects the slave address and selects the comm unication format. sar can be written and read only when the ice bit is cleared to 0 in iccr. bit bit name initial value r/w description 7 6 5 4 3 2 1 sva6 sva5 sva4 sva3 sva2 sva1 sva0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w slave address 6 to 0 sets a slave address 0 fs 0 r/w selects the communi cation format together with the fsx bit in sarx. refer to table 15.2. 15.3.3 second slave address register (sarx) sarx stores the second slave address and se lects the communication format. sarx can be written and read only when the ice bit is cleared to 0 in iccr. bit bit name initial value r/w description 7 6 5 4 3 2 1 svax6 svax5 svax4 svax3 svax2 svax1 svax0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w slave address 6 to 0 sets the second slave address 0 fsx 0 r/w selects the communica tion format together with the fs bit in sar. refer to table 15.2.
section 15 i 2 c bus interface (iic) rev. 6.00 mar. 24, 2006 page 239 of 412 rej09b0142-0600 table 15.2 communication format sar sarx fs fsx i 2 c transfer format 0 0 sar and sarx are used as the slave addresses with the i 2 c bus format. 0 1 only sar is used as the slave address with the i 2 c bus format. 1 0 only sarx is used as the slave address with the i 2 c bus format. 1 1 clock synchronous serial format (sar and sarx are invalid) 15.3.4 i 2 c bus mode register (icmr) the i 2 c bus mode register (icmr) se ts the transfer format and tr ansfer rate. it can only be accessed when the ice bit in iccr is 1. bit bit name initial value r/w description 7 mls 0 r/w msb-first/lsb-first select 0: msb-first 1: lsb-first set this bit to 0 when the i 2 c bus format is used. 6 wait 0 r/w wait insertion bit this bit is valid only in master mode with the i 2 c bus format. when wait is set to 1, after the fall of the clock for the final data bit, the iric flag is set to 1 in iccr, and a wait state begins (with scl at the low level). when the iric flag is cleared to 0 in iccr, the wait ends and the acknowledge bit is transferred. if wait is cleared to 0, data and acknowledge bits are transferred consecutively with no wait in serted. the iric flag in iccr is set to 1 on completion of the acknowledge bit transfer, regardless of the wait setting. 5 4 3 cks2 cks1 cks0 0 0 0 r/w r/w r/w serial clock select 2 to 0 this bit is valid only in master mode. these bits select the required transfer rate, together with the iicx bit in tscr. refer table 15.3.
section 15 i 2 c bus interface (iic) rev. 6.00 mar. 24, 2006 page 240 of 412 rej09b0142-0600 bit bit name initial value r/w description 2 1 0 bc2 bc1 bc0 0 0 0 r/w r/w r/w bit counter 2 to 0 these bits specify the number of bits to be transferred next. with the i 2 c bus format, the data is transferred with one addition acknowledge bit. bit bc2 to bc0 settings should be made during an interval between transfer frames. if bits bc2 to bc0 are set to a value other than 000, the setting should be made while the scl line is low. the value returns to 000 at the end of a data transfer, including the acknowledge bit. i 2 c bus format clocked synchronous mode 000: 9 000: 8 001: 2 001: 1 010: 3 010: 2 011: 4 011: 3 100: 5 100: 4 101: 6 101: 5 110: 7 110: 6 111: 8 111: 7
section 15 i 2 c bus interface (iic) rev. 6.00 mar. 24, 2006 page 241 of 412 rej09b0142-0600 table 15.3 i 2 c transfer rate tscr icmr bit 0 bit 5 bit 4 bit 3 transfer rate iicx cks2 cks1 cks0 clock = 5 mhz = 8 mhz = 10 mhz = 16 mhz 0 0 0 0 /28 179mhz 286khz 357khz 571khz 0 0 0 1 /40 125khz 200khz 250khz 400khz 0 0 1 0 /48 104khz 167khz 208khz 333khz 0 0 1 1 /64 78.1khz 125khz 156khz 250khz 0 1 0 0 /80 62.5khz 100khz 125khz 200khz 0 1 0 1 /100 50.0khz 80.0khz 100khz 160khz 0 1 1 0 /112 44.6khz 71.4khz 89.3khz 143khz 0 1 1 1 /128 39.1khz 62.5khz 78.1khz 125khz 1 0 0 0 /56 89.3khz 143khz 179khz 286khz 1 0 0 1 /80 62.5khz 100khz 125khz 200khz 1 0 1 0 /96 52.1khz 83.3khz 104khz 167khz 1 0 1 1 /128 39.1khz 62.5khz 78.1khz 125khz 1 1 0 0 /160 31.3khz 50.0khz 62.5khz 100khz 1 1 0 1 /200 25.0khz 40.0khz 50.0khz 80.0khz 1 1 1 0 /224 22.3khz 35.7khz 44.6khz 71.4khz 1 1 1 1 /256 19.5khz 31.3khz 39.1khz 62.5khz
section 15 i 2 c bus interface (iic) rev. 6.00 mar. 24, 2006 page 242 of 412 rej09b0142-0600 15.3.5 i 2 c bus control register (iccr) i 2 c bus control register (iccr) consists of the control bits and interrupt request flags of i 2 c bus interface. bit bit name initial value r/w description 7 ice 0 r/w i 2 c bus interface enable when this bit is set to 1, the i 2 c bus interface module is enabled to send/receive data and drive the bus since it is connected to the scl and sda pins. icmr and icdr can be accessed. when this bit is cleared, the module is halted and separated from the scl and sda pins. sar and sarx can be accessed. 6 ieic 0 r/w i 2 c bus interface interrupt enable when this bit is 1, interrupts are enabled by iric. 5 4 mst trs 0 0 r/w r/w master/slave select transmit/receive select 00: slave receive mode 01: slave transmit mode 10: master receive mode 11: master transmit mode both these bits will be cleared by hardware when they lose in a bus contention in master mode of the i 2 c bus format. in slave receive mode , the r/w bit in the first frame immediately after the start automatically sets these bits in receive mode or transmit mode by using hardware. the settings can be made again for the bits that were set/cleared by hardware, by reading these bits. when the trs bit is intended to change during a transfer, the bit will not be switched until the frame transfer is completed, including acknowledgement.
section 15 i 2 c bus interface (iic) rev. 6.00 mar. 24, 2006 page 243 of 412 rej09b0142-0600 bit bit name initial value r/w description 3 acke 0 r/w acknowledge bit judgement selection 0: the value of the acknowledge bit is ignored, and continuous transfer is per formed. the value of the received acknowledge bit is not indicated by the ackb bit, which is always 0. 1: if the acknowledge bit is 1, continuous transfer is interrupted. 2 bbsy 0 r/w bus busy in slave mode, reading the bbsy flag enables to confirm whether the i 2 c bus is occupied or released. the bbsy flag is set to 0 when the sda level changes from high to low under the condition of scl = high, assuming that the start condition has been issued. the bbsy flag is cleared to 0 when the sda level changes from low to high under the condition of scl = high, assuming that the start condition has been issued. writing to the bbsy flag in slave mode is disabled. in master mode, the bbsy flag is used to issue start and stop conditions. write 1 to bbsy and 0 to scp to issue a start condition. follow this procedure when also re-transmitting a start condition. to issue a start/stop condition, use the mov instruction. the i 2 c bus interface must be set in master transmit mode before the issue of a start condition.
section 15 i 2 c bus interface (iic) rev. 6.00 mar. 24, 2006 page 244 of 412 rej09b0142-0600 bit bit name initial value r/w description 1 iric 0 r/w i 2 c bus interface interrupt request flag also see table 15.4. [setting conditions] in master mode with i 2 c bus format ? when a start condition is detected in the bus line state after a start condition is issued ? when a wait is inserted between the data and acknowledge bit when wait = 1 ? at the rising edge of the ni nth transfer/receive clock, and at the falling edge of the eighth transfer/receive clock when a wait is inseted ? when a slave address is received after bus arbitration is lost (when the al flag is set to1) ? when 1 is received as the acknowledge bit when the acke bit is 1 (when the ackb bit is set to 1) i 2 c bus format slave mode ? when the slave address (sva, svax) matches (when the aas and aasx flags are set to 1) and at the end of data transfer up to the subsequent retransmission start condition or stop condition detection (fs = 0 and when the tdre or rdrf flag is set to 1) ? when the general call address is detected (when the adz flag is set to 1) and at the end of data transfer up to the subsequent retransmission start condition or stop condition detection (when the tdre or rdrf flag is set to 1) ? when 1 is received as the acknowledge bit when the acke bit is 1 (when the ackb bit is set to 1) ? when a stop condition is detected (when the stop or estp flag is set to 1) clocked synchronous serial format ? at the end of data transfer (when the tdre or rdrf flag is set to 1) ? when a start condition is detected with serial format selected [clearing condition] when 0 is written in iric after reading iric = 1
section 15 i 2 c bus interface (iic) rev. 6.00 mar. 24, 2006 page 245 of 412 rej09b0142-0600 bit bit name initial value r/w description 0 scp 1 w start condition/stop condition prohibit the scp bit controls the i ssue of start/stop conditions in master mode. to issue a start condition, write 1 in bbsy and 0 in scp. a retransmit start condition is issued in the same way. to issue a stop condition, write 0 in bbsy and 0 in scp. this bit is always read as 1. if 1 is written, the data is not stored. 15.3.6 i 2 c bus status register (icsr) the i 2 c bus status register (icsr) consists of status flags. also see table 15.4. bit bit name initial value r/w description 7 estp 0 r/w error stop condition detection flag this bit is valid in i 2 c bus format slave mode. [setting condition] when a stop condition is detected during frame transfer. [clearing conditions] ? when 0 is written in estp after reading estp = 1 ? when the iric flag is cleared to 0 6 stop 0 r/w normal stop condition detection flag this bit is valid in i 2 c bus format slave mode. [setting condition] when a stop condition is detected during frame transfer. [clearing conditions] ? when 0 is written in stop after reading stop = 1 ? when the iric flag is cleared to 0
section 15 i 2 c bus interface (iic) rev. 6.00 mar. 24, 2006 page 246 of 412 rej09b0142-0600 bit bit name initial value r/w description 5 irtr 0 r/w i 2 c bus interface continuous transmission/reception interrupt request flag [setting conditions] in i 2 c bus interface slave mode ? when the tdre or rdrf flag is set to 1 when aasx = 1 in i 2 c bus interface other modes ? when the tdre or rdrf flag is set to 1 [clearing conditions] ? when 0 is written in irtr after reading irtr = 1 ? when the iric flag is cleared to 0 4 aasx 0 r/w second slave address recognition flag [setting condition] when the second slave address is detected in slave receive mode and fsx = 0 [clearing conditions] ? when 0 is written in aasx after reading aasx = 1 ? when a start condition is detected ? in master mode 3 al 0 r/w arbitration lost [setting condition] when bus arbitration was lost in master mode. [clearing conditions] ? when 0 is written in al after reading al = 1 ? when icdr data is written (transmit mode) or read (receive mode)
section 15 i 2 c bus interface (iic) rev. 6.00 mar. 24, 2006 page 247 of 412 rej09b0142-0600 bit bit name initial value r/w description 2 aas 0 r/w slave addr ess recognition flag [setting condition] when the slave address or general call address is detected in slave receive mode and fs = 0. [clearing conditions] ? when icdr data is written (transmit mode) or read (receive mode) ? when 0 is written in aas after reading aas = 1 ? in master mode 1 adz 0 r/w general call address recognition flag this bit is valid in i 2 c bus format slave receive mode. [setting condition] when the general call address is detected in slave receive mode and fsx = 0 or fs = 0. [clearing conditions] ? when icdr data is written (transmit mode) or read (receive mode) ? when 0 is written in adz after reading adz = 1 ? in master mode 0 ackb 0 r/w acknowledge bit in transmit mode, the acknowledge data that are returned by the receive devi ce is loaded. in receive mode, the acknowledge data originally specified to this bit is sent to the transmit device, after receiving data. when this bit is read, the loaded value (return value from the receive device) is read at transmission and the specified value is read at reception.
section 15 i 2 c bus interface (iic) rev. 6.00 mar. 24, 2006 page 248 of 412 rej09b0142-0600 15.3.7 timer serial co ntrol register (tscr) the timer serial control register (tscr) is an 8- bit readable/writable register that controls the operating modes. bit bit name initial value r/w description 7 to 2 ? all 1 ? reserved this bit is always read as 1 and cannot be modified. 1 iicrst 0 r/w i 2 c control unit reset resets the control unit except for the i 2 c registers. when a hang up occurs due to illegal communication during i 2 c operation, setting iicrst to 1 can set a port or reset the i 2 c control unit without in itializing registers. 0 iicx 0 r/w i 2 c transfer rate select selects the transfer rate in master mode, together with bits cks2 to cks0 in ic mr. refer to table 15.3. when, with the i 2 c bus format selected, iric is set to 1 an d an interrupt is generated, other flags must be checked in order to identify the source th at set iric to 1. although each source has a corresponding flag, cau tion is needed at the end of a transf er. when the tdre or rdrf internal flag is set, the readable irtr fl ag may or may not be set. even wh en the iric flag and irtr flag are set, the tdre or rdrf internal flag may not be set. table 15.4 shows the relationship between the flags and the transfer states.
section 15 i 2 c bus interface (iic) rev. 6.00 mar. 24, 2006 page 249 of 412 rej09b0142-0600 table 15.4 flags and transfer states mst trs bbsy estp stop irtr aasx al aas adz ackb state 1/0 1/0 0 0 0 0 0 0 0 0 0 idle state (flag clearing required) 1 1 0 0 0 0 0 0 0 0 0 start condition issuance 1 1 1 0 0 1 0 0 0 0 0 start condition established 1 1/0 1 0 0 0 0 0 0 0 0/1 master mode wait 1 1/0 1 0 0 1 0 0 0 0 0/1 master mode transmit/receive end 0 0 1 0 0 0 1/0 1 1/0 1/0 0 arbitration lost 0 0 1 0 0 0 0 0 1 0 0 sar matc h by first frame in slave mode 0 0 1 0 0 0 0 0 1 1 0 general call address match 0 0 1 0 0 0 1 0 0 0 0 sarx match 0 1/0 1 0 0 0 0 0 0 0 0/1 slave mode transmit/receive end (except after sarx match) 0 0 1/0 1 1 1 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 1 slave mode transmit/receive end (after sarx match) 0 1/0 0 1/0 1/0 0 0 0 0 0 0/ 1 stop condition detected 15.4 operation the i 2 c bus interface has serial and i 2 c bus formats. 15.4.1 i 2 c bus data format the i 2 c bus formats are addressing formats and an acknowledge bit is inserted. these are shown in figures 15.3. figure 15.5 shows the i 2 c bus timing. the first frame following a start condition always consists of 8 bits.
section 15 i 2 c bus interface (iic) rev. 6.00 mar. 24, 2006 page 250 of 412 rej09b0142-0600 s sla r/ w a data a a/ a p 111 1 n 7 1 m (a) i 2 c bus format (fs = 0 or fsx = 0) (b) i 2 c bus format (start condition retransmission, fs = 0 or fsx = 0) n: transfer bit count (n = 1 to 8) m: transfer frame count (m 1) s sla r/ w a data 11 1 n1 7 1 m1 s sla r/ w a data a/ a p 11 1 n2 7 1 m2 1 1 1 a/ a n1 and n2: transfer bit count (n1 and n2 = 1 to 8) m1 and m2: transfer frame count (m1 and m2 1) 11 figure 15.3 i 2 c bus data formats (i 2 c bus formats) sda scl s 1-7 sla 8 r/ w 9 a 1-7 data 89 1-7 89 a data p a/ a figure 15.4 i 2 c bus timing [legend] s: start condition. the master device driv es sda from high to low while scl is high sla: slave address r/ w : indicates the direction of data transfer: fr om the slave device to the master device when r/ w is 1, or from the master device to the slave device when r/ w is 0 a: acknowledge. the receiving device drives sda data: transferred data p: stop condition. the master device driv es sda from low to high while scl is high
section 15 i 2 c bus interface (iic) rev. 6.00 mar. 24, 2006 page 251 of 412 rej09b0142-0600 15.4.2 master transmit operation when data is set to icdr during the period between the execution of an instruction to issue a start condition and the creation of the start condition, the data may not be output normally, because there will be a contention between a generation of a start condition and an output of data. although data h'ff is to be sent to the icdr re gister by a dummy write op eration before an issue of a stop condition, the h'ff data may be output by the dummy write operation if the execution of the instruction to issue a stop condition is delayed. to prevent these problems, follow the flowchart shown below during the master transmit operation. in i 2 c bus format master transmit mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowle dge signal. the transmission procedure and operations synchronize with the icdr writing are described below. 1. set the ice bit in iccr to 1. set bits mls, wait, and cks2 to cks0 in icmr, and bit iicx in tscr, according to the operating mode. 2. read the bbsy flag in iccr to confirm that the bus is free. 3. set bits mst and trs to 1 in i ccr to select master transmit mode. 4. write 1 to bbsy and 0 to scp. this change s sda from high to low when scl is high, and generates the start condition. 5. then iric and irtr flags are set to 1. if the ieic bit in iccr has been set to 1, an interrupt request is sent to the cpu. 6. write the data (slave address + r/ w ) to icdr. with the i 2 c bus format (when the fs bit in sar or the fsx bit in sarx is 0), the first frame data following the start condition indicates the 7-bit slave addr ess and transmit/receive direction. as indicating the end of the transfer, and so the iric flag is cleared to 0. after writing icdr, clear iric continuously not to execute other interrupt handling routine. if one frame of data has been transmitted before the iric clearing, it can not be determine the end of tran smission. the master device sequentially sends the transmission clock and the data written to icdr using the timing shown in figure 15.5. the selected slave device (i.e. the slave device with the matching slave addres s) drives sda low at the 9th transmit clock pulse and returns an acknowledge signal. 7. when one frame of data has been transmitted, the iric flag is set to 1 at the rise of the 9th transmit clock pulse. after one frame has been transmitted scl is automatically fixed low in synchronization with the internal clock until the next transmit data is written. 8. read the ackb bit in icsr to confirm that ac kb is cleared to 0. when the slave device has not acknowledged (ackb bit is 1), operate the step [12] to end transmission, and retry the transmit operation.
section 15 i 2 c bus interface (iic) rev. 6.00 mar. 24, 2006 page 252 of 412 rej09b0142-0600 9. write the transmit data to icdr. as indicating th e end of the transfer, and so the iric flag is cleared to 0. perform the icdr write and the iric flag clearing sequentially, just as in the step [6]. transmission of the next frame is performed in synchronization with the internal clock. 10. when one frame of data has been transmitted, the iric flag is set to 1 at the rise of the 9th transmit clock pulse. after one frame has been transmitted scl is automatically fixed low in synchronization with the internal clock until the next transmit data is written. 11. read the ackb bit in icsr. confirm that the slave device has been acknowledged (ackb bit is 0). when there is data to be transmitted, go to the step [9] to continue next transmission. when the slave device has not acknowledged (ackb bit is set to 1), operate the step [12] to end transmission. 12. clear the iric flag to 0. and write 0 to bbsy and scp in iccr. this changes sda from low to high when scl is high, and generates the stop condition. sda (master output) sda (slave output) 2 1 2 1 4 36 58 79 bit 7 slave address bit 6 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 iric irtr icdr scl (master output) start condition generation data 1 address + r/ w [4] write bbsy = 1 and scp = 0 (start condition issuance) [9] iric clearance [9] icdr write [6] iric clearance user processing slave address data 1 r/ w [7] [5] a [6] icdr write normal operation icdr writing prohibited note: * data write timing in icdr * figure 15.5 master transmit mode operation timing example (mls = wait = 0)
section 15 i 2 c bus interface (iic) rev. 6.00 mar. 24, 2006 page 253 of 412 rej09b0142-0600 15.4.3 master receive operation the data buffer of the i 2 c module can receive data consecutively since it consists of icdrr and icdrs. however, if the completion of receiving the last data is delayed, there will be a contention between the instruction to issue a stop condition an d the scl clock output to receive the next data, and may generate unnecessary clocks or fix the output level of the sda line as low. the switch timing of the ackb bit in the icsr register sh ould be controlled because the acknowledge bit does not return acknowledgement after receiving the last data in master mode. these problems can be avoided by using the wait function. follow the flowchart shown below. in master receive mode, the master device outputs th e receive clock, receives data, and returns an acknowledge signal. the slave device transmits da ta. the reception procedure and operations with the wait function synchronized w ith the icdr read operation to receive data in sequence are shown below. 1. clear the trs bit in iccr to 0 to switch from transmit mode to receive mode, and set the wait bit in icmr to 1. also clear the bit in icsr to ackb 0 (acknowledge data setting). 2. when icdr is read (dummy data read), recep tion is started, and the receive clock is output, and data received, in synchronization with the inte rnal clock. in order to detect wait operation, set the iric flag in iccr must be cleared to 0. after reading icdr, clear iric continuously not to execute other interrupt ha ndling routine. if one frame of data has been received before the iric clearing, it can not be determine the end of reception. 3. the iric flag is set to 1 at the fall of the 8t h receive clock pulse. if the ieic bit in iccr has been set to 1, an interrupt request is sent to the cpu. scl is automatically fixed low in synchronization with the internal clock until the ir ic flag clearing. if the first frame is the last receive data, execute the st ep [10] to halt reception. 4. clear the iric flag to release from the wait state. the master device outputs the 9th clock and drives sda at the 9th receive clock pu lse to return an acknowledge signal. 5. when one frame of data has been received, th e iric flag in iccr and the irtr flag in icsr are set to 1 at the rise of the 9th receive cl ock pulse. the master devi ce outputs scl clock to receive next data. 6. read icdr. 7. clear the iric flag to detect next wait operation. data reception process from the step [5] to [7] should be executed during one byte reception peri od after iric flag clearing in the step [4] or [9] to release wait status. 8. the iric flags set to 1 at the fall of 8th recei ve clock pulse. scl is automatically fixed low in synchronization with the internal clock until the iric flag clearing. if this frame is the last receive data, execute the st ep [10] to halt reception.
section 15 i 2 c bus interface (iic) rev. 6.00 mar. 24, 2006 page 254 of 412 rej09b0142-0600 9. clear the iric flag in iccr to cancel wait operation. the master device outputs the 9th clock and drives sda at the 9th receive clock pulse to return an ackowledge signal. data can be received continuously by repe ating the step [5] to [9]. 10. set the ackb bit in icsr to 1 so as to return ?no acknowledge? data. also set the trs bit in iccr to 1 to switch from receive mode to transmit mode. 11. clear iric flag to 0 to release from the wait state. 12. when one frame of data has b een received, the iric flag is set to 1 at the rise of the 9th receive clock pulse. 13. clear the wait bit to 0 to switch from wait mode to no wait mode. read icdr and the iric flag to 0. clearing of the iric flag should be af ter the wait = 0. if the wait bit is cleared to 0 after clearing the iric flag and then an instruction to issue a stop condition is executed, the stop condition cannot be issued because the output level of th e sda line is fixed as low. 14. clear the bbsy bit and scp bit to 0. this changes sda from low to high when scl is high, and generates the stop condition. sda (master output) sda (slave output) 2 1 2 1 4 36 58 79 bit 7 bit 6 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 iric irtr icdr scl (master output) data 1 [1] trs cleared to 0 wait set to 1 ackb cleared to 0 [7] iric clearance [6] icdr read (data 1) [4] iric clearance [2] iric clearance user processing bit 5 bit 4 bit 3 5 4 3 9 data 1 data 2 [3] [5] a [2] icdr read (dummy read) master tansmit mode master receive mode a figure 15.6 master receive mode operation timing example (1) (mls = ackb = 0, wait = 1)
section 15 i 2 c bus interface (iic) rev. 6.00 mar. 24, 2006 page 255 of 412 rej09b0142-0600 sda (master output) sda (slave output) 2 1 2 1 4 36 58 79 bit 7 bit 6 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 iric irtr icdr scl (master output) data 3 [9] iric clearance [7] iric clearance [9] iric clearance [6] icdr read (data 3) [7] iric clearance user processing 9 8 data 3 data 4 [8] [5] [8] [5] a a [6] icdr read (data 2) bit 0 data 2 data 2 data 1 figure 15.6 master receive mode operation timing example (2) (mls = ackb = 0, wait = 1) 15.4.4 slave receive operation in slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. th e reception procedure and operations in slave receive mode are described below. 1. set the ice bit in iccr to 1. set the mls bit in icmr and the mst and trs bits in iccr according to the operating mode. 2. when the start condition output by the master device is detected, the bbsy flag in iccr is set to 1. 3. when the slave address matches in the first frame following the start condition, the device operates as the slave device specified by th e master device. if the 8th data bit (r/ w ) is 0, the trs bit in iccr remains cleared to 0, an d slave receive operation is performed. 4. at the 9th clock pulse of th e receive frame, the slave device drives sda low and returns an acknowledge signal. at the same time, the iric flag in iccr is set to 1. if the ieic bit in iccr has been set to 1, an interrupt request is sent to the cpu. if the rdrf internal flag has been cleared to 0, it is set to 1, and the receive operation continues. if the rdrf internal flag has been set to 1 and ninth clock is received fo r the following data receival, the slave device drives scl low from the falling edge of the receive clock until data is read into icdr.
section 15 i 2 c bus interface (iic) rev. 6.00 mar. 24, 2006 page 256 of 412 rej09b0142-0600 5. read icdr and clear the iric flag in iccr to 0. the rdrf flag is cleared to 0. receive operations can be performed continuously by repeating steps [4] and [5]. when sda is changed from low to high when scl is high, and the stop condition is detected, the bbsy flag in iccr is cleared to 0. sda (master output) sda (slave output) 2 1 2 1 4 36 58 79 bit 7 bit 6 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 iric icdrs icdrr rdrf scl (master output) start condition issuance scl (slave output) interrupt request generation address + r/ w address + r/ w [5] icdr read [5] iric clearance user processing slave address data 1 [4] a r/ w high figure 15.7 example of slave r eceive mode operation timing (1) (mls = ackb = 0)
section 15 i 2 c bus interface (iic) rev. 6.00 mar. 24, 2006 page 257 of 412 rej09b0142-0600 sda (master output) sda (slave output) 2 14 36 58 79 8 79 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 1 bit 0 iric icdrs icdrr rdrf scl (master output) scl (slave output) interrupt request generation interrupt request generation data 2 data 2 data 1 data 1 [5] icdr read [5] iric clearance user processing data 2 data 1 [4] [4] a figure 15.8 example of slave r eceive mode operation timing (2) (mls = ackb = 0)
section 15 i 2 c bus interface (iic) rev. 6.00 mar. 24, 2006 page 258 of 412 rej09b0142-0600 15.4.5 slave transmit operation in slave transmit mode, the slave device outputs th e transmit data, while the master device outputs the receive clock and returns an acknowledge si gnal. the transmission procedure and operations in slave transmit mode are described below. 1. set the ice bit in iccr to 1. set the mls bit in icmr and the mst and trs bits in iccr according to the operating mode. 2. when the slave address matches in the first frame following detection of the start condition, the slave device drives sda low at the 9th cloc k pulse and returns an acknowledge signal. at the same time, the iric flag in iccr is set to 1. if the ieic bit in iccr has been set to 1, an interrupt request is sent to the cpu. if the 8th data bit (r/ w ) is 1, the trs bit in iccr is set to 1, and the mode changes to slave transmit mode automatically. the tdre internal flag is set to 1. the slave device drives sc l low from the fall of the transmit clock until icdr data is written. 3. after clearing the iric flag to 0, write data to icdr. the tdre internal flag is cleared to 0. the written data is transferred to icdrs, and the tdre internal flag and the iric and irtr flags are set to 1 again. after clearing the iric flag to 0, write the next data to icdr. the slave device sequentially sends the data written into icdr in accordance with the clock output by the master device at the timing shown in figure 15.9. 4. when one frame of data has been transmitted, th e iric flag in iccr is set to 1 at the rise of the 9th transmit clock pulse. if the tdre intern al flag has been set to 1, this slave device drives scl low from the fall of the transmit cl ock until data is written to icdr. the master device drives sda low at the 9th clock pulse, and returns an acknowledge signal. as this acknowledge signal is stored in the ackb bit in icsr, this bit can be used to determine whether the transfer operation was performed norm ally. when the tdre inte rnal flag is 0, the data written into icdr is transferred to icdrs, transmission is started, and the tdre internal flag and the iric and irtr flags are set to 1 again. 5. to continue transmission, clear the iric flag to 0, then write the next data to be transmitted into icdr. the tdre fl ag is cleared to 0. transmit operations can be performed continuously by repeating steps [4] and [5]. to end transmission, write h'ff to icdr. when sda is changed from low to high when scl is high, and the stop condition is detected, the bbsy flag in iccr is cleared to 0.
section 15 i 2 c bus interface (iic) rev. 6.00 mar. 24, 2006 page 259 of 412 rej09b0142-0600 sda (slave output) sda (master output) scl (slave output) 2 1 2 1 4 36 58 79 9 8 bit 7 bit 6 bit 5 bit 7 bit 6 bit 4 bit 3 bit 2 bit 1 bit 0 iric icdrs icdrt tdre scl (master output) interrupt request generation interrupt request generation interrupt request generation slave receive mode slave transmit mode data 1 data 2 [3] iric clearance [5] iric clearance [3] icdr write [3] icdr write [5] icdr write user processing data 1 data 1 data 2 data 2 a r/ w a [3] [2] figure 15.9 example of slave transmit mode operation timing (mls = 0) s data data p 1 1 n 8 1 m fs = 1 and fsx = 1 n: transfer bit count (n = 1 to 8) m: transfer frame count (m 1) figure 15.10 i 2 c bus data format (serial format) 15.4.6 clock synchronous serial format serial format is a non-addressing format that has no acknowledge bit. figure 15.10 shows this format.
section 15 i 2 c bus interface (iic) rev. 6.00 mar. 24, 2006 page 260 of 412 rej09b0142-0600 15.4.7 iric setting ti ming and scl control the interrupt request flag (iric) is set at differ ent times depending on the wait bit in icmr, the fs bit in sar, and the fsx bit in sarx. if the tdre or rdrf internal flag is set to 1, scl is automatically held low after one fr ame has been transferred; this ti ming is synchronized with the internal clock. figure 15.11 shows the iric set timing and scl control. (a) when wait = 0, and fs = 0 or fsx = 0 (i 2 c bus format, no wait) scl sda iric user processing clear iric write to icdr (transmit) or read icdr (receive) 1 a 8 1 1 a 7 1 89 7 (b) when wait = 1, and fs = 0 or fsx = 0 (i 2 c bus format, wait inserted) scl sda iric user processing clear iric clear iric write to icdr (transmit) or read icdr (receive) scl sda iric user processing (c) when fs = 1 and fsx = 1 (synchronous serial format) clear iric write to icdr (transmit) or read icdr (receive) 8 89 8 7 1 8 7 1 figure 15.11 iric setting timing and scl control
section 15 i 2 c bus interface (iic) rev. 6.00 mar. 24, 2006 page 261 of 412 rej09b0142-0600 15.4.8 noise canceler the logic levels at the scl and sda pins are routed through noise cancelers before being latched internally. figure 15.12 shows a block diagram of the noise canceler circuit. the noise canceler consists of two cascaded la tches and a match detector. the scl (or sda) input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree. if they do not agree, the previous value is held. system clock period sampling clock c dq latch c dq latch scl or sda input signal match detector internal scl or sda signal sampling clock figure 15.12 block di agram of noise canceler
section 15 i 2 c bus interface (iic) rev. 6.00 mar. 24, 2006 page 262 of 412 rej09b0142-0600 15.4.9 sample flowcharts figures 15.13 to 15.16 show sample flowcharts for using the i 2 c bus interface in each mode. start initialize set mst = 1 and trs = 1 in iccr write bbsy =1 and scp = 0 in iccr write transmit data in icdr clear iric in iccr no no yes yes yes yes no no [1] initialization [3] select master transmit mode. [4] start condition issuance [6] set transmit data for the first byte (slave address + r/ w ). (after writing icdr, clear iric continuously) [9] set transmit data for the second and subsequent bytes. (after writing icdr, clear iric immediately) [2] test the status of the scl and sda lines. [7] wait for 1 byte to be transmitted. [10] wait for 1 byte to be transmitted. [11] test for end of tranfer [12] stop condition issuance [8] test the acknowledge bit, transferred from slave device. [5] wait for a start condition read iric in iccr read ackb in icsr iric = 1? ackb = 0? transmit mode? write transmit data in icdr clear iric in iccr read iric in iccr read ackb in icsr clear iric in iccr end of transmission? or ackb = 1? write bbsy = 0 and scp = 0 in iccr end read bbsy in iccr bbsy = 0? yes no read iric in iccr iric = 1? yes no yes no iric = 1? master receive mode figure 15.13 sample flowchar t for master transmit mode
section 15 i 2 c bus interface (iic) rev. 6.00 mar. 24, 2006 page 263 of 412 rej09b0142-0600 master receive operation clear iric in iccr yes no yes yes no yes no [1] select receive mode. [3] wait for 1 byte to be received. [4] clear iric. (to end the wait insertion) [6] read the receive data. [9] clear iric. (to end the wait insertion) [2] start receiving. the first read is a dummy read. after reading icdr, please clear iric immediately. [7] clear iric. [10] set acknowledge data for the last reception. [11] clear iric. (to end the wait insertion) [12] wait for 1 byte to be received. [13] clear wait mode. read receive data. clear iric. (note: after setting wait = 0, iric should be cleared to 0.) [14] stop condition issuance. [8] wait for the next data to be received. [5] wait for 1 byte to be received. read iric in iccr read icdr clear iric in iccr iric = 1? iric = 1? yes last receive? last receive? set ackb = 1 in icsr set trs = 1 in iccr clear iric in iccr read iric in iccr set wait = 0 in icmr read icdr clear iric in iccr write bbsy = 0 and scp = 0 in iccr end set trs = 0 in iccr set ackb = 0 in icsr read iric in iccr iric = 1? yes no no read iric in iccr clear iric in iccr no iric = 1? set wait = 1 in icmr clear iric in iccr read icdr figure 15.14 sample flowch art for master receive mode
section 15 i 2 c bus interface (iic) rev. 6.00 mar. 24, 2006 page 264 of 412 rej09b0142-0600 start initialize set mst = 0 and trs = 0 in iccr set ackb = 0 in icsr read iric in iccr iric = 1? yes no clear iric in iccr read aas and adz in icsr aas = 1 and adz = 0? read trs in iccr trs = 0? no yes no yes yes no yes yes no no [1] [2] [3] [4] [5] [6] [7] [8] last receive? read icdr read iric in iccr iric = 1? clear iric in iccr set ackb = 1 in icsr read icdr read iric in iccr read icdr iric = 1? clear iric in iccr end general call address processing * description omitted slave transmit mode [1] select slave receive mode. [2] wait for the first byte to be received (slave address). [3] start receiving. the first read is a dummy read. [4] wait for the transfer to end. [5] set acknowledge data for the last reception. [6] start the last reception. [7] wait for the transfer to end. [8] read the last receive data. figure 15.15 sample flowch art for slave receive mode
section 15 i 2 c bus interface (iic) rev. 6.00 mar. 24, 2006 page 265 of 412 rej09b0142-0600 slave transmit mode write transmit data in icdr read iric in iccr iric = 1? clear iric in iccr clear iric in iccr clear iric in iccr read ackb in icsr set trs = 0 in iccr end of transmission (ackb = 1)? yes no no yes end [1] [2] [3] read icdr [5] [4] [1] set transmit data for the second and subsequent bytes. [2] wait for 1 byte to be transmitted. [3] test for end of transfer. [4] set slave receive mode. [5] dummy read (to release the scl line). figure 15.16 sample flowchart for slave transmit mode
section 15 i 2 c bus interface (iic) rev. 6.00 mar. 24, 2006 page 266 of 412 rej09b0142-0600 15.5 usage notes 1. in master mode, if an instruction to generate a start condition is immediately followed by an instruction to generate a stop condition, neither condition will be output correctly. to output consecutive start and stop conditi ons, after issuing the instruction that generates the start condition, read the relevant ports, check that scl and sda are both low, then issue the instruction that generates the stop condition. note that scl may not yet have gone low when bbsy is cleared to 0. 2. either of the following two conditions will st art the next transfer. pay attention to these conditions when reading or writing to icdr. ? ? table 15.5 i 2 c bus timing (scl and sda output) item symbol output timing unit notes scl output cycle time t sclo 28t cyc to 256t cyc ns scl output high pulse width t sclho 0.5t sclo ns scl output low pulse width t scllo 0.5t sclo ns sda output bus free time t bufo 0.5t sclo ? 1t cyc ns start condition output hold time t staho 0.5t sclo ? 1t cyc ns retransmission start condition output setup time t staso 1t sclo ns stop condition output setup time t stoso 0.5t sclo + 2t cyc ns data output setup time (master) t sdaso 1t scllo ? 3t cyc ns data output setup time (slave) 1t scll ? 3t cyc ns data output hold time t sdaho 3t cyc ns 4. scl and sda inputs are sampled in synchronization with the internal clock. the ac timing therefore depends on the system clock cycle t cyc , as shown in table 20-4 in section 20, electrical characteristics. note that the i 2 c bus interface ac timing specifications will not be met with a system clock frequency of less than 5 mhz.
section 15 i 2 c bus interface (iic) rev. 6.00 mar. 24, 2006 page 267 of 412 rej09b0142-0600 5. the i 2 c bus interface specification for the scl rise time t sr is under 1000 ns (300 ns for high- speed mode). in master mode, the i 2 c bus interface monitors the scl line and synchronizes one bit at a time during communication. if t sr (the time for scl to go from low to v ih ) exceeds the time determined by the input clock of the i 2 c bus interface, the high period of scl is extended. the scl rise time is determined by the pull-up resistance an d load capacitance of the scl line. to insure proper operation at the set transfer rate, adjust the pull-up resistance and load capacitance so that the scl rise time does not exceed the values given in the table in table 15.6. table 15.6 permissible scl rise time (t sr ) values time indication iicx t cyc indication i 2 c bus specification (max.) = 5 mhz = 8 mhz = 10 mhz = 16 mhz 0 7.5t cyc normal mode 1000 ns 1000 ns 937 ns 750 ns 468 ns high-speed mode 300 ns 300 ns 300 ns 300 ns 300 ns 1 17.5t cyc normal mode 1000 ns 1000 ns 1000 ns 1000 ns 1000 ns high-speed mode 300 ns 300 ns 300 ns 300 ns 300 ns 6. the i 2 c bus interface specifications for the scl and sd a rise and fall times are under 1000 ns and 300 ns. the i 2 c bus interface scl and sda output timing is prescribed by t scyc and t cyc , as shown in table 15.5. however, because of the rise and fall times, the i 2 c bus interface specifications may not be satisfied at the maxi mum transfer rate. table 15.7 shows output timing calculations for different operating frequencies, including the worst-case influence of rise and fall times. the values in the above table will vary depending on the settings of the iicx bit and bits cks0 to cks2. depending on the frequency it may not be possible to achieve the maximum transfer rate; therefore, whether or not the i 2 c bus interface specifications are met must be determined in accordance with the actual setting conditions. t bufo fails to meet the i 2 c bus interface specifications at any fr equency. the solution is either (a) to provide coding to secure the necessary inte rval (approximately 1 s) between issuance of a stop condition and issuance of a start condition, or (b) to select devices whose input timing permits this output timing for use as slave devices connected to the i 2 c bus. t scllo in high-speed mode and t staso in standard mode fail to satisfy the i 2 c bus interface specifications for worst- case calculations of t sr /t sf . possible solutions that should be investigated include (a) adjusting the rise and fall times by means of a pull-up resistor and capacitive load, (b) reducing the tr ansfer rate to meet the specifications, or (c) selecting devices whose input timing permits this output timing for use as slave devices connected to the i 2 c bus.
section 15 i 2 c bus interface (iic) rev. 6.00 mar. 24, 2006 page 268 of 412 rej09b0142-0600 table 15.7 i 2 c bus timing (with maximum influence of t sr /t sf ) time indication (at maximum transfer rate) [ns] item t cyc indication t sr /t sf influence (max.) i 2 c bus specifi- cation (min.) = 5 mhz = 8 mhz = 10 mhz = 16 mhz t sclho 0.5t sclo (?t sr ) standard mode ?1000 4000 4000 4000 4000 4000 high-speed mode ?300 600 950 950 950 950 t scllo 0.5t sclo (?t sf ) standard mode ?250 4700 4750 4750 4750 4750 high-speed mode ?250 1300 1000 * 1 1000 * 1 1000 * 1 1000 * 1 t bufo 0.5t sclo ?1t cyc standard mode ?1000 4700 3800 * 1 3875 * 1 3900 * 1 3938 * 1 ( ?t sr ) high-speed mode ?300 1300 750 * 1 825 * 1 850 * 1 888 * 1 t staho 0.5t sclo ?1t cyc standard mode ?250 4000 4550 4625 4650 4688 (?t sf ) high-speed mode ?250 600 800 875 900 938 t staso 1t sclo (?t sr ) standard mode ?1000 4700 9000 9000 9000 9000 high-speed mode ?300 600 2200 2200 2200 2200 t stoso 0.5t sclo + 2t cyc standard mode ?1000 4000 4400 4250 4200 4125 (?t sr ) high-speed mode ?300 600 1350 1200 1150 1075 t sdaso 1t scllo * 2 ?3t cyc standard mode ?1000 250 3100 3325 3400 3513 (master) (?t sr ) high-speed mode ?300 100 400 625 700 813 t sdaso 1t scll * 2 ?3t cyc standard mode ?1000 250 3100 3325 3400 3513 (slave) (?t sr ) high-speed mode ?300 100 400 625 700 813 t sdaho 3t cyc standard mode 0 0 600 375 300 188 high-speed mode 0 0 600 375 300 188 notes: 1. does not meet the i 2 c bus interface specification 2. calculated using the i 2 c bus specification values (standard mode: 4700 ns min.; high- speed mode: 1300 ns min.).
section 15 i 2 c bus interface (iic) rev. 6.00 mar. 24, 2006 page 269 of 412 rej09b0142-0600 7. note on icdr read at end of master reception to halt reception after completion of a receive operation in master receive mode, set the trs bit to 1 and write 0 to bbsy and scp in iccr. this changes the sda pin from low to high when the scl pin is high, and generates the stop condition. after this, receive data can be read by means of an icdr read, but if data remains in the buffer the icdrs receive data will not be transferred to icdr, and so it will not be possibl e to read the second byte of data. if it is necessary to read the second byte of data, issue the stop condition in master receive mode (i.e. with the trs bit cleared to 0). when reading the receive da ta, first confirm that the bbsy bit in iccr is cleared to 0, the stop condition has been generated, and the bus has been released, then read icdr with trs cleared to 0. note that if the receive data (icdr data) is read in the interval between execution of the instruction for issuance of the stop condition (writing of 0 to bbsy and scp in iccr) and the actual generation of the stop condition, the clock may not be output correctly in subsequent master transmission. 8. notes on start condition issuance for retransmission depending on the timing combination with the start condition issuance and the subsequently writing data to icdr, it may not be possible to issue the retransmission and the data transmission after retransmission condition issuance. after start condition issuance is done and dete rmined the start condition, write the transmit data to icdr, as shown below. figure 15.17 shows the timing of start condition issuance for retransmission, and the timing for subsequently writing data to icdr, together with the corresponding flowchart.
section 15 i 2 c bus interface (iic) rev. 6.00 mar. 24, 2006 page 270 of 412 rej09b0142-0600 sda iric scl ack bit 7 data output [3] (restart) start condition instruction issuance [4] iric determination [5] icdr write (next transmit data) [2] detemination of scl = low [1] iric determination start condition (retransmission) iric = 1? yes clear iric in icsr read scl pin write transmit data to icdr write bbsy = 1, scp = 0 (icsr) [1] [1] wait for end of 1-byte transfer [2] determine whether scl is low [3] issue restart condition instruction for transmission [4] determine whether start condition is generated or not [5] set transmit data (slave address + r/ w ) [2] [3] [4] [5] yes yes no no iric = 1? yes scl = low? start condition issuance? no no other processing note: program so that processing from [3] to [5] is executed continuously. 9 figure 15.17 flowchart and timing of start condition instruction issuance for retransmission
section 15 i 2 c bus interface (iic) rev. 6.00 mar. 24, 2006 page 271 of 412 rej09b0142-0600 ? ? ? ? scl bc2 to bc0 1 9 a transmit/receive data transmit/receive data a 23 1 9 scl = 'l' confirm iric clear iric flag clear available iric flag clear available iric flag clear unavailable when bc2 to bc0 2 clear iric 23 45678 sda 7 065 765 4321 0 iric (operation example) figure 15.18 iric flag clea r timing on wait operation
section 15 i 2 c bus interface (iic) rev. 6.00 mar. 24, 2006 page 272 of 412 rej09b0142-0600 ? ? sda scl trs bit rdrf bit icdrs data full (c) trs = 0 (b) rdrf = 0 (a) icdrs data full icdr read trs = 0 setting stop condition start condition data a address a 89 123456789 123 cancel condition of scl = low fixation is set. along with icdrs icdrr transfer detection of 9th clock rise (trs = 1) figure 15.19 notes on icdr reading with trs = 1 setting in master mode
section 15 i 2 c bus interface (iic) rev. 6.00 mar. 24, 2006 page 273 of 412 rej09b0142-0600 sda scl trs bit tdre bit (b) trs = 1 (a) tdre = 0 trs = 0 setting icdr write automatic trs = 1 setting by receiving r/w = 1 start condition stop condition data a address a 89 1234567891234 cancel condition of scl = low fixation is set. along with icdrt icdrr transfer figure 15.20 notes on icdr writing with trs = 0 setting in slave mode ?
section 15 i 2 c bus interface (iic) rev. 6.00 mar. 24, 2006 page 274 of 412 rej09b0142-0600
section 16 a/d converter rev. 6.00 mar. 24, 2006 page 275 of 412 rej09b0142-0600 section 16 a/d converter this lsi includes a successive approximation type 10-bit a/d converter that allows up to eight analog input channels to be selected. the block diagram of the a/d converter is shown in figure 16.1. 16.1 features ? ? ? ? ? ? ? ? ? ? ? ? ? ?
section 16 a/d converter rev. 6.00 mar. 24, 2006 page 276 of 412 rej09b0142-0600 module data bus control circuit internal data bus 10-bit d/a comparator + sample-and- hold circuit adi interrupt bus interface successive approximations register analog multiplexer a d c s r a d c r a d d r d a d d r c a d d r b a d d r a an0 an1 an2 an3 an4 an5 an6 an7 [legend] adcr: a/d control register adcsr: a/d control/status register addra: a/d data register a addrb: a/d data register b addrc: a/d data register c addrd: a/d data register d note: an4, an5, an6, and an7 do not exist in the 42-pin version. adtrg /4 /8 av cc * figure 16.1 block di agram of a/d converter
section 16 a/d converter rev. 6.00 mar. 24, 2006 page 277 of 412 rej09b0142-0600 16.2 input/output pins table 16.1 summarizes the input pins used by the a/d converter. the eigh t analog input pins are divided into two groups; analog input pins 0 to 3 (an0 to an3) comprising group 0, analog input pins 4 to 7 (an4 to an7) comprising group 1. the avcc pin is the power supply pin for the analog block in the a/d converter. table 16.1 pin configuration pin name symbol i/o function analog power supply pin av cc input analog block power supply pin analog input pin 0 an0 input analog input pin 1 an1 input analog input pin 2 an2 input analog input pin 3 an3 input group 0 analog input pins analog input pin 4 an4 input analog input pin 5 an5 input analog input pin 6 an6 input analog input pin 7 an7 input group 1 analog input pins a/d external trigger input pin adtrg input external trigger input pin for starting a/d conversion
section 16 a/d converter rev. 6.00 mar. 24, 2006 page 278 of 412 rej09b0142-0600 16.3 register description the a/d converter has the following registers. ? ? ? ? ? ? 16.3.1 a/d data registers a to d (addra to addrd) there are four 16-bit read-only addr registers; addra to addrd, used to store the results of a/d conversion. the addr registers, which st ore a conversion result for each channel, are shown in table 16.2. the converted 10-bit data is stored in bits 6 to 15. the lower 6 bits are always read as 0. the data bus between the cpu and the a/d converter is 8 bits wide. the upper byte can be read directly from the cpu, however the lower byte should be r ead via a temporary register. the temporary register cont ents are transferred from the addr when the upper byte data is read. therefore, byte access to addr shou ld be done by reading the upp er byte first then the lower one. word access is also possible. addr is initialized to h'0000. table 16.2 analog input channels and corresponding addr registers analog input channel group 0 group 1 a/d data register to be stored results of a/d conversion an0 an4 addra an1 an5 addrb an2 an6 addrc an3 an7 addrd
section 16 a/d converter rev. 6.00 mar. 24, 2006 page 279 of 412 rej09b0142-0600 16.3.2 a/d control/status register (adcsr) adcsr consists of the control bits and conversion end status bits of the a/d converter. bit bit name initial value r/w description 7 adf 0 r/w a/d end flag [setting conditions] ? when a/d conversion ends in single mode ? when a/d conversion ends on all the channels selected in scan mode [clearing condition] when 0 is written after reading adf = 1 6 adie 0 r/w a/d interrupt enable a/d conversion end interrupt (adi) request enabled by adf when 1 is set 5 adst 0 r/w a/d start setting this bit to 1 starts a/d conversion. in single mode, this bit is cleared to 0 automatically when conversion on the specified channel is complete. in scan mode, conversion continues sequentially on the specified channels until this bit is cleared to 0 by software, a reset, or a transition to standby mode. 4 scan 0 r/w scan mode selects single mode or scan mode as the a/d conversion operating mode. 0: single mode 1: scan mode 3 cks 0 r/w clock select selects the a/d conversions time 0: conversion time = 134 states (max.) 1: conversion time = 70 states (max.) clear the adst bit to 0 before switching the conversion time.
section 16 a/d converter rev. 6.00 mar. 24, 2006 page 280 of 412 rej09b0142-0600 bit bit name initial value r/w description 2 1 0 ch2 ch1 ch0 0 0 0 r/w r/w r/w channel select 0 to 2 select analog input channels. when scan = 0 when scan = 1 000: an0 000: an0 001: an1 001: an0 to an1 010: an2 010: an0 to an2 011: an3 011: an0 to an3 100: an4 100: an4 101: an5 101: an4 to an5 110: an6 110: an4 to an6 111: an7 111: an4 to an7 an4, an5, an6, and an7 do not exist in the 42-pin version. 16.3.3 a/d control register (adcr) adcr enables a/d conversion started by an external trigger signal. bit bit name initial value r/w description 7 trge 0 r/w trigger enable a/d conversion is started at the falling edge and the rising edge of the external trigger signal ( adtrg ) when this bit is set to 1. the selection between the falling edge and rising edge of the external trigger pin ( adtrg ) conforms to the wpeg5 bit in the interrupt edge select register 2 (iegr2). 6 to 1 ? all 1 ? reserved these bits are always read as 1. 0 ? 0 r/w reserved do not set this bit to 1, though the bit is readable/writable.
section 16 a/d converter rev. 6.00 mar. 24, 2006 page 281 of 412 rej09b0142-0600 16.4 operation the a/d converter operates by su ccessive approximation with 10-b it resolution. it has two operating modes; single mode and scan mode. when changing the operating mode or analog input channel, in order to prevent in correct operation, first clear th e bit adst to 0 in adcsr. the adst bit can be set at the same time as the opera ting mode or analog input channel is changed. 16.4.1 single mode in single mode, a/d conversion is performed once for the analog input on the specified single channel as follows: 1. a/d conversion is started when the adst bit in adcsr is set to 1, according to software or external trigger input. 2. when a/d conversion is completed, the resu lt is transferred to the corresponding a/d data register to the channel. 3. on completion of conversion, the adf bit in adcsr is set to 1. if the adie bit is set to 1 at this time, an adi interrupt request is generated. 4. the adst bit remains set to 1 during a/d conversion. when a/d conversion ends, the adst bit is automatically cleared to 0 and the a/d converter enters the wait state. 16.4.2 scan mode in scan mode, a/d conversion is performed sequentially for the analog input on the specified channels (four channels maximum) as follows: 1. when the adst bit is set to 1 by software, or external trigger input, a/d conversion starts on the first channel in the group (an0 when ch2 = 0, an4 when ch2 = 1). 2. when a/d conversion for each channel is comple ted, the result is sequentially transferred to the a/d data register corresponding to each channel. 3. when conversion of all the selected channels is completed, the adf flag in adcsr is set to 1. if the adie bit is set to 1 at this time, an adi interrupt is requested. conversion of the first channel in the group starts again. 4. the adst bit is not automatically cleared to 0. steps [2] to [3] are re peated as long as the adst bit remains set to 1. when the adst bi t is cleared to 0, a/ d conversion stops.
section 16 a/d converter rev. 6.00 mar. 24, 2006 page 282 of 412 rej09b0142-0600 16.4.3 input sampling and a/d conversion time the a/d converter has a built-in sample-and-hold circuit. the a/d converter samples the analog input when the a/d conversion start delay time (t d ) has passed after the adst bit is set to 1, then starts conversion. figure 16.2 shows the a/d conversion timing. table 16.3 shows the a/d conversion time. as indicated in figure 16.2, th e a/d conversion time includes t d and the input sampling time. the length of t d varies depending on the timing of the wr ite access to adcsr. the total conversion time therefore varies w ithin the ranges indicated in table 16.3. in scan mode, the values given in table 16.3 apply to the first conversion time. in the second and subsequent conversions, the conversion time is 128 states (fixed) when cks = 0 and 66 states (fixed) when cks = 1. (1) (2) address write signal input sampling timing adf [legend] (1): adcsr write cycle (2): adcsr address t d : a/d conversion start delay t spl : input sampling time t conv : a/d conversion time figure 16.2 a/d conversion timing
section 16 a/d converter rev. 6.00 mar. 24, 2006 page 283 of 412 rej09b0142-0600 table 16.3 a/d conversio n time (single mode) cks = 0 cks = 1 item symbol min typ max min typ max a/d conversion start delay t d 6 ? 9 4 ? 5 input sampling time t spl ? 31 ? ? 15 ? a/d conversion time t conv 131 ? 134 69 ? 70 note: all values represent the number of states. 16.4.4 external tr igger input timing the a/d conversion can also be started by an external trigger input. when the trge bit is set to 1 in adcr, external trigger input is enabled at the adtrg pin. a falling edge at the adtrg input pin sets the adst bit to 1 in adcsr, starting a/d conversion. other operations, in both single and scan modes, are the same as when the bit adst has been set to 1 by software. figure 16.3 shows the timing. adtrg internal trigger signal adst a/d conversion figure 16.3 external trigger input timing
section 16 a/d converter rev. 6.00 mar. 24, 2006 page 284 of 412 rej09b0142-0600 16.5 a/d conversion accuracy definitions this lsi's a/d conversion accuracy definitions are given below. ? ? ? ? ? ?
section 16 a/d converter rev. 6.00 mar. 24, 2006 page 285 of 412 rej09b0142-0600 111 110 101 100 011 010 001 000 1 8 2 8 6 8 7 8 fs quantization error digital output ideal a/d conversion characteristic analog input voltage 3 8 4 8 5 8 figure 16.4 a/d conversio n accuracy definitions (1) fs digital output ideal a/d conversion characteristic nonlinearity error analog input voltage offset error actual a/d conversion characteristic full-scale error figure 16.5 a/d conversio n accuracy definitions (2)
section 16 a/d converter rev. 6.00 mar. 24, 2006 page 286 of 412 rej09b0142-0600 16.6 usage notes 16.6.1 permissible si gnal source impedance this lsi's analog input is designed such that conv ersion accuracy is guarant eed for an input signal for which the signal source impedance is 5 k ? ? ? 16.6.2 influences on absolute accuracy adding capacitance results in coupling with gnd, and therefor e noise in gnd may adversely affect absolute accuracy. be sure to make the connection to an electrically stable gnd. care is also required to ensure that filter circuits do not interfere with digital signals or act as antennas on the mounting board. 20 pf 10 k ? c in = 15 pf sensor output impedance to 5 k ? this lsi low-pass filter c to 0.1 f sensor input a/d converter equivalent circuit figure 16.6 analog input circuit example
section 17 eeprom rev. 6.00 mar. 24, 2006 page 287 of 412 rej09b0142-0600 section 17 eeprom this lsi has an on-chip 512-byte eeprom. the block diagram of the eeprom is shown in figure 17.1. 17.1 features ? ? ? ? ? ? ?
section 17 eeprom rev. 6.00 mar. 24, 2006 page 288 of 412 rej09b0142-0600 h'0000 h'01ff h'ff09 h'ff10 esar sda eeprom data bus eeprom key register (ekr) key control circuit i 2 c bus interface control circuit address bus y decoder y-select/ sense amp. memory array user area (512 bytes) slave address register power-on reset booster circuit eeprom module esar: register for referring the slave address (specifies the slave address of the memory array) [legend] x decoder scl figure 17.1 block diagram of eeprom
section 17 eeprom rev. 6.00 mar. 24, 2006 page 289 of 412 rej09b0142-0600 17.2 input/output pins pins used in the eeprom are listed in table 17.1. table 17.1 pin configuration pin name symbol input/ output function serial clock pin scl input the scl pin is used to cont rol serial input/output data timing. the data is input at the rising edge of the clock and output at the falling edge of the clock. the scl pin needs to be pulled up by resistor as that pin is o pen-drain driven structure of the i 2 c pin. use proper resistor value for your system by considering v ol , i ol , and the c in pin capacitance in section 20.2.2, dc characteristics and in section 20.2.3, ac characteristics. maximum clock frequency is 400 khz. serial data pin sda input/ output the sda pin is bidirectional for serial data transfer. the sda pin needs to be pulled up by resistor as that pin is open-drain driven structure. use proper resi stor value for your system by considering v ol , i ol , and the c in pin capacitance in section 20.2.2, dc characteristics and in section 20.2.3, ac characteristics. except for a start condition and a stop condition which will be discussed later, the high-to-low and low-to-high change of sda input should be done during scl low periods. 17.3 register description the eeprom has a following register. ? 17.3.1 eeprom key register (ekr) ekr is an 8-bit readable/writable register, whic h changes the slave address code written in the eeprom. the slave address code is changed by writing h'5f in ekr and then writing either of h'00 to h'07 as an address code to the h'ff09 address in the eeprom by the byte write method. ekr is initialized to h'ff.
section 17 eeprom rev. 6.00 mar. 24, 2006 page 290 of 412 rej09b0142-0600 17.4 operation 17.4.1 eeprom interface this lsi has a multi-chip structure with two internal chips of f-ztat? hd64f3664 and 512- byte eeprom. the eeprom interface is the i 2 c bus interface. this i 2 c bus is open to th e outside, so the communication with the external devices connected to the i 2 c bus can be made. 17.4.2 bus format and timing the i 2 c bus format and the i 2 c bus timing follow section 15.4.1, i 2 c bus data format. the bus formats specific for the eeprom are the following two. 1. the eeprom address is configured of two bytes, the write data is transferred in the order of upper address and lower address from each msb side. 2. the write data is transmitted from the msb side. the bus format and bus timing of the eeprom are shown in figure 17.2. r/ w ack scl sda start condition slave address upper memory address lower memory address data data stop conditon [legend] r/ w : r/ w code (0 is for a write and 1 is for a read), ack: acknowledge ack ack ack ack 11 2345678 a15 a8 a7 a0 d7 d0 d7 d0 91 89 1 89 1 89 8 9 figure 17.2 eeprom bus format and bus timing
section 17 eeprom rev. 6.00 mar. 24, 2006 page 291 of 412 rej09b0142-0600 17.4.3 start condition a high-to-low transition of the sda input with the scl input high is needed to generate the start condition for starting read, write operation. 17.4.4 stop condition a low-to-high transition of the sda input with the scl input high is needed to generate the stop condition for stopping read, write operation. the standby operation starts afte r a read sequence by a stop co ndition. in th e case of write operation, a stop condition terminat es the write data inputs and pl ace the device in an internally- timed write cycle to the memories. after the internally-timed write cycle (t wc ) which is specified as t wc , the device enters a standby mode. 17.4.5 acknowledge all address data and serial data su ch as read data and write data are transmitted to and from in 8- bit unit. the acknowledgement is the signal that indicates that this 8-bit data is normally transmitted to and from. in the write operation, eeprom sends "0" to ac knowledge in the ninth cy cle after receiving the data. in the read operation, eeprom sends a read data following the acknowledgement after receiving the data. after sending read data, the eeprom enters the bus open state. if the eeprom receives "0" as an acknowle dgement, it sends read data of the next address. if the eeprom does not receive acknowledgement "0" and receives a fo llowing stop cond ition, it stops the read operation and enters a standby mode. if the eeprom receives neither acknowledgement "0" nor a stop condition, the eeprom keeps bus open without sending read data.
section 17 eeprom rev. 6.00 mar. 24, 2006 page 292 of 412 rej09b0142-0600 17.4.6 slave addressing the eeprom device receives a 7-bit slave address and a 1-bit r/ w code following the generation of the start conditions. the eeprom enables the ch ip for a read or a write operation with this operation. the slave address consists of a former 4-bit device code and latter 3-bit slave address as shown in table 17.2. the device code is used to distinguish device type and this lsi uses "1010" fixed code in the same manner as in a general-purpose eepro m. the slave address code selects one device out of all devices with device code 1010 (8 devices in maximum) which are connected to the i 2 c bus. this means that the device is selected if the inputted slave address code received in the order of a2, a1, a0 is equal to th e corresponding slave address reference register (esar). the slave address code is stored in the address h'ff09 in the eepro m. it is transferred to esar from the slave address register in the memory arra y during 10 ms after the reset is released. an access to the eeprom is not allowed during transfer. the initial value of the slave address code written in the eeprom is h'00. it can be written in the range of h'00 to h'07. be sure to write the data by the byte write method. the next one bit of the slave address is the r/ w code. 0 is for a write and 1 is for a read. the eeprom turns to a standby state if the devi ce code is not "1010" or slave address code doesn?t coincide. table 17.2 slave addresses bit bit name initial value setting value remarks 7 device code d3 ? 1 6 device code d2 ? 0 5 device code d1 ? 1 4 device code d0 ? 0 3 slave address code a2 0 a2 the initial value can be changed 2 slave address code a1 0 a1 the initial value can be changed 1 slave address code a0 0 a0 the initial value can be changed
section 17 eeprom rev. 6.00 mar. 24, 2006 page 293 of 412 rej09b0142-0600 17.4.7 write operations there are two types write operati ons; byte write operation and page write operation. to initiate the write operation, input 0 to r/ w code following the slave address. 1. byte write a write operation requires an 8-bit data of a 7-bit slave address with r/ w code = "0". then the eeprom sends acknowledgement "0" at the ninth bit. this enters the write mode. then, two bytes of the memory address are received fr om the msb side in the order of upper and lower. upon receipt of one-b yte memory address, the eepr om sends acknowledgement "0" and receives a following a one-byte write data. after receipt of write data, the eeprom sends acknowledgement "0". if the eeprom receives a stop c ondition, the eeprom enters an internally controlled write cycle and termin ates receipt of scl and sda inputs until completion of the write cycle. the eeprom re turns to a standby mode after completion of the write cycle. the byte write operation is shown in figure 17.3. r/ w ack scl sda ack ack ack 11 2345678 a15 a8 a7 a0 d7 d0 91 89 1 89 8 9 start condition upper memory address lower memory address write data slave address stop conditon [legend] r/ w : r/ w code (0 is for a write and 1 is for a read) ack: acknowledge figure 17.3 byte write operation 2. page write this lsi is capable of the page write operatio n which allows any number of bytes up to 8 bytes to be written in a single write cycle. the write data is input in the same sequence as the byte write in the order of a st art condition, slave address + r/ w code, memory address (n), and write data (dn) with every ninth bit acknowledgement "0" output. the eeprom enters the page write operation if the eeprom receives mo re write data (dn+1) is input instead of receiving a stop condition after receiving the write data (dn). lsb 3 bits (a2 to a0) in the eeprom address are automatically incremented to be the (n+1) address upon receiving write data (dn+1). thus the write data can be received sequentially.
section 17 eeprom rev. 6.00 mar. 24, 2006 page 294 of 412 rej09b0142-0600 addresses in the page are incremented at each r eceipt of the write data and the write data can be input up to 8 bytes. if the lsb 3 bits (a 2 to a0) in the eeprom address reach the last address of the page, the address will roll over to the first address of the same page. when the address is rolled over, write data is received tw ice or more to the same address, however, the last received data is valid. at the receipt of the stop condition, write data reception is terminated and the write operation is entered. the page write operation is shown in figure 17.4. scl sda 11 2345678 a15 a8 a7 a0 d7 d0 d7 d0 91 89 1 89 8 9 r/ w ack ack ack ack ack start condition upper memory address lower memory address write data write data stop conditon [legend] slave address r/ w : r/ w code (0 is for a write and 1 is for a read), ack: acknowledge figure 17.4 page write operation 17.4.8 acknowledge polling acknowledge polling feature is used to show if the eeprom is in an internally-timed write cycle or not. this feature is initiated by the input of the 8-bit slave address + r/ w code following the start condition during an internally-timed write cycle. acknowledge polling will operate r/w code = "0". the ninth acknowledgement judges if the eeprom is an intern ally-timed write cycle or not. acknowledgement "1" shows the eeprom is in a internally-timed write cycle and acknowledgement "0" shows the internally-timed write cycle has been completed. the acknowledge polling starts to function after a write da ta is input, i.e., when the stop condition is input.
section 17 eeprom rev. 6.00 mar. 24, 2006 page 295 of 412 rej09b0142-0600 17.4.9 read operation there are three read operations; current address re ad, random address read, and sequential read. read operations are initiated in the same way as write operations with the exception of r/w = 1. 1. current address read the internal address counter maintains the (n+1) address that is made by the last address (n) accessed during the last read or write operation, with incremented by one. current address read accesses the (n+1) address kept by the internal address counter. after receiving in the order of a star t condition and the slave address + r/ w code (r/w = 1), the eeprom outputs the 1-byte data of the (n+1) address from the most significant bit following acknowledgement "0". if the eepro m receives in the orde r of acknowledgement "1" and a following stop condition, the eeprom stops the read operation and is turned to a standby state. in case the eeprom has accessed the last addr ess h'01ff at previous read operation, the current address will roll over and returns to zero address. in case the eeprom has accessed the last address of the page at previous write ope ration, the current address will roll over within page addressing and returns to the first address in the same page. the current address is valid while power is on . the current address after power on will be undefined. after power is turned on, define the address by the random address read operation described below is necessary. the current address read operation is shown in figure 17.5. r/ w ack scl sda d7 d0 ack 11 23456789 8 9 start condition stop conditon [legend] r/ w : r/ w code (0 is for a write and 1 is for a read) ack: acknowledge read data slave address figure 17.5 current address read operation
section 17 eeprom rev. 6.00 mar. 24, 2006 page 296 of 412 rej09b0142-0600 2. random address read this is a read operation with defined read address. a random address read requires a dummy write to set read address. the eeprom re ceives a start condition, slave address + r/ w code (r/ w = 0), memory address (upper) and memory address (lower) sequentially. the eeprom outputs acknowledgement "0" after receiving memory address (low er) then enters a current address read with receiving a start condition again. the eepro m outputs the read data of the address which was defined in the dummy write operation. after receiving acknowledgement "1" and a following stop condition, the eeprom stops the random read operation and returns to a standby state. the random address read operation is shown in figure 17.6. sda a15 a8 a7 a0 d7 d0 r/ w ack scl ack ack 11 23456789 1 89 89 11 23456789 8 9 rack ack start condition start condition upper memory address lower memory address stop conditon [legend] slave address slave address read data r/ w : r/ w code (0 is for a write and 1 is for a read), ack: acknowledge figure 17.6 random address read operation 3. sequential read this is a mode to read the data sequentially. da ta is sequential read by either a current address read or a random address read. if the eepr om receives acknowledgem ent "0" after 1-byte read data is output, the read address is incremented and the next 1-byte read data are coming out. data is output sequentially by incremen ting addresses as long as the eeprom receives acknowledgement "0" after the data is output. the address will roll over and returns address zero if it reaches the last address h'01ff. the sequ ential read can be continued after roll over. the sequential read is terminated if th e eeprom receives acknowledgement "1" and a following stop condition as the same manner as in the random address read. the condition of a sequential read when the current address read is used is shown in figure 17.7.
section 17 eeprom rev. 6.00 mar. 24, 2006 page 297 of 412 rej09b0142-0600 scl sda 11 2345678 d7 d0 d7 d0 98918 9 r/ w ack ack ack start condition stop conditon [legend] r/ w : r/ w code (0 is for a write and 1 is for a read) ack: acknowledge read data read data slave address figure 17.7 sequential read operation (when current address read is used) 17.5 usage notes 17.5.1 data protection at v cc on/off when v cc is turned on or off, the data might be destroyed by malfunction. be careful of the notices described below to prevent the data to be destroyed. 1. scl and sda should be fixed to v cc or v ss during v cc on/off. 2. v cc should be turned off after the eep rom is placed in a standby state. 3. when v cc is turned on from the intermediate level, malfunction is caused, so v cc should be turned on from the ground level (v ss ). 4. v cc turn on speed should be longer than 10 us. 17.5.2 write/erase endurance the endurance is 10 5 cycles/page (1% cumulative failure ra te) in case of page programming and 10 4 cycles/byte in case of byte programming. the data retention time is more than 10 years when a device is page-programmed less than 10 4 cycles.
section 17 eeprom rev. 6.00 mar. 24, 2006 page 298 of 412 rej09b0142-0600 17.5.3 noise suppression time this eeprom has a noise suppression function at scl and sda inputs, that cuts noise of width less than 50 ns. be careful not to allow noise of width more than 50 ns because the noise of with more than 50 ms is rec ognized as an active pulse.
section 18 power supply circuit rev. 6.00 mar. 24, 2006 page 299 of 412 rej09b0142-0600 section 18 power supply circuit this lsi incorporates an internal power supply step-down circuit. use of this circuit enables the internal power supply to be fixed at a constant level of approximately 3.0 v, independently of the voltage of the power supply connected to the external v cc pin. as a result, the current consumed when an external power supply is used at 3.0 v or above can be held down to virtually the same low level as when used at approxim ately 3.0 v. if the external power supply is 3.0 v or below, the internal voltage will be practically the same as th e external voltage. it is, of course, also possible to use the same level of external power supply voltage and internal power supply voltage without using the internal power supply step-down circuit. 18.1 when using internal power supply step-down circuit connect the external po wer supply to the v cc pin, and connect a capacita nce of approximately 0.1 f between v cl and v ss , as shown in figure 18.1. the internal step-down circuit is made effective simply by adding this external circuit. in the ex ternal circuit interface, th e external power supply voltage connected to v cc and the gnd potential connected to v ss are the reference levels. for example, for port input/output levels, the v cc level is the reference for the high level, and the v ss level is that for the low level. the a/d converter analog power supply is not affected by the internal step-down circuit. v cl v ss internal logic step-down circuit internal power supply stabilization capacitance (approx. 0.1 f) v cc v cc = 3.0 to 5.5 v figure 18.1 power supply connection when internal step-down circuit is used
section 18 power supply circuit rev. 6.00 mar. 24, 2006 page 300 of 412 rej09b0142-0600 18.2 when not using internal power supply step-down circuit when the internal power supply step-down circuit is not used, connect the external power supply to the v cl pin and v cc pin, as shown in figure 18.2. the external power supply is then input directly to the internal power supply. the permissible range for the power supply voltage is 3.0 v to 3.6 v. operation cannot be guaranteed if a voltage outside this range (less than 3.0 v or more than 3.6 v) is input. v cl v ss internal logic step-down circuit internal power supply v cc v cc = 3.0 to 3.6 v figure 18.2 power supply connection when internal step-down circuit is not used
section 19 list of registers rev. 6.00 mar. 24, 2006 page 301 of 412 rej09b0142-0600 section 19 list of registers the register list gives information on the on-chip i/o register addresses, how the register bits are configured, and the register states in each operating mode. the information is given as shown below. 1. register addresses (address order) ? ? ? ? ? ? ? ? ? ?
section 19 list of registers rev. 6.00 mar. 24, 2006 page 302 of 412 rej09b0142-0600 19.1 register addresses (address order) the data bus width indicates the numbers of bits by which the register is accessed. the number of access states indicates the number of states based on the sp ecified reference clock. register name abbre- viation bit no. address module name data bus width access state timer mode register w tmrw 8 h'ff80 timer w 8 2 timer control register w tcrw 8 h'ff81 timer w 8 2 timer interrupt enable register w tierw 8 h'ff82 timer w 8 2 timer status register w tsrw 8 h'ff83 timer w 8 2 timer i/o control register 0 tior0 8 h'ff84 timer w 8 2 timer i/o control register 1 tior1 8 h'ff85 timer w 8 2 timer counter tcnt 16 h'ff86 timer w 16 * 1 2 general register a gra 16 h'ff88 timer w 16 * 1 2 general register b grb 16 h'ff8a timer w 16 * 1 2 general register c grc 16 h'ff8c timer w 16 * 1 2 general register d grd 16 h'ff8e timer w 16 * 1 2 flash memory control register 1 flmcr1 8 h'ff90 rom 8 2 flash memory control register 2 flmcr2 8 h'ff91 rom 8 2 flash memory power control register flpwcr 8 h'ff92 rom 8 2 erase block register 1 ebr1 8 h'ff93 rom 8 2 flash memory enable register fenr 8 h'ff9b rom 8 2 timer control register v0 tcrv0 8 h'ffa0 timer v 8 3 timer control/status register v tcsrv 8 h'ffa1 timer v 8 3 timer constant register a tcora 8 h'ffa2 timer v 8 3 timer constant register b tcorb 8 h'ffa3 timer v 8 3 timer counter v tcntv 8 h'ffa4 timer v 8 3 timer control register v1 tcrv1 8 h'ffa5 timer v 8 3 timer mode register a tma 8 h'ffa6 timer a 8 2 timer counter a tca 8 h'ffa7 timer a 8 2 serial mode register smr 8 h'ffa8 sci3 8 3 bit rate register brr 8 h'ffa9 sci3 8 3 serial control register 3 scr3 8 h'ffaa sci3 8 3
section 19 list of registers rev. 6.00 mar. 24, 2006 page 303 of 412 rej09b0142-0600 register name abbre- viation bit no. address module name data bus width access state transmit data register tdr 8 h'ffab sci3 8 3 serial status register ssr 8 h'ffac sci3 8 3 receive data register rdr 8 h'ffad sci3 8 3 a/d data register a addra 16 h'ffb0 a/d converter 8 3 a/d data register b addrb 16 h'ffb2 a/d converter 8 3 a/d data register c addrc 16 h'ffb4 a/d converter 8 3 a/d data register d addrd 16 h'ffb6 a/d converter 8 3 a/d control/status register adcsr 8 h'ffb8 a/d converter 8 3 a/d control register adcr 8 h'ffb9 a/d converter 8 3 timer control/status register wd tcsrwd 8 h'ffc0 wdt * 2 8 2 timer counter wd tcwd 8 h'ffc1 wdt * 2 8 2 timer mode register wd tmwd 8 h'ffc2 wdt * 2 8 2 i 2 c bus control register iccr 8 h'ffc4 iic 8 2 i 2 c bus status register icsr 8 h'ffc5 iic 8 2 i 2 c bus data register icdr 8 h'ffc6 iic 8 2 second slave address register sarx 8 h'ffc6 iic 8 2 i 2 c bus mode register icmr 8 h'ffc7 iic 8 2 slave address register sar 8 h'ffc7 iic 8 2 address break control register abr kcr 8 h'ffc8 address break 8 2 address break status register abr ksr 8 h'ffc9 address break 8 2 break address register h barh 8 h'ffca address break 8 2 break address register l barl 8 h'ffcb address break 8 2 break data register h bdrh 8 h'ffcc address break 8 2 break data register l bdrl 8 h'ffcd address break 8 2 port pull-up control register 1 pucr1 8 h'ffd0 i/o port 8 2 port pull-up control register 5 pucr5 8 h'ffd1 i/o port 8 2 port data register 1 pdr1 8 h'ffd4 i/o port 8 2 port data register 2 pdr2 8 h'ffd5 i/o port 8 2 port data register 5 pdr5 8 h'ffd8 i/o port 8 2 port data register 7 pdr7 8 h'ffda i/o port 8 2 port data register 8 pdr8 8 h'ffdb i/o port 8 2
section 19 list of registers rev. 6.00 mar. 24, 2006 page 304 of 412 rej09b0142-0600 register name abbre- viation bit no. address module name data bus width access state port data register b pdrb 8 h'ffdd i/o port 8 2 port mode register 1 pmr1 8 h'ffe0 i/o port 8 2 port mode register 5 pmr5 8 h'ffe1 i/o port 8 2 port control register 1 pcr1 8 h'ffe4 i/o port 8 2 port control register 2 pcr2 8 h'ffe5 i/o port 8 2 port control register 5 pcr5 8 * 3 h'ffe8 i/o port 8 2 port control register 7 pcr7 8 h'ffea i/o port 8 2 port control register 8 pcr8 8 h'ffeb i/o port 8 2 system control register 1 syscr1 8 h'fff0 power-down 8 2 system control register 2 syscr2 8 h'fff1 power-down 8 2 interrupt edge select register 1 iegr1 8 h'fff2 interrupts 8 2 interrupt edge select register 2 iegr2 8 h'fff3 interrupts 8 2 interrupt enable register 1 ienr1 8 h'fff4 interrupts 8 2 interrupt flag register 1 irr1 8 h'fff6 interrupts 8 2 wake-up interrupt flag register iwpr 8 h'fff8 interrupts 8 2 module standby control register 1 mstcr1 8 h'fff9 power-down 8 2 timer serial control register tscr 8 h'fffc iic 8 2 notes: 1. only word access can be used. 2. wdt: watchdog timer. 3. the number of bits is six for h8/3664n. ? eeprom register name abbre- viation bit no. address module name data bus width access state eeprom key register ekr 8 h'ff10 ieeprom 8 2
section 19 list of registers rev. 6.00 mar. 24, 2006 page 305 of 412 rej09b0142-0600 19.2 register bits register bit names of the on-chip peripheral modules are described below. each line covers eight bits, and 16-bit registers are shown as 2 lines. register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name tmrw cts ? bufeb bufea ? pwmd pwmc pwmb timer w tcrw cclr cks2 cks1 cks0 tod toc tob toa tierw ovie ? ? ? imied imiec imieb imiea tsrw ovf ? ? ? imfd imfc imfb imfa tior0 ? iob2 iob1 iob0 ? ioa2 ioa1 ioa0 tior1 ? iod2 iod1 iod0 ? ioc2 ioc1 ioc0 tcnt tcnt15 tcnt14 tcnt13 tcnt12 tcnt11 tcnt10 tcnt9 tcnt8 tcnt7 tcnt6 tcnt5 tcnt4 tcnt3 tcnt2 tcnt1 tcnt0 gra gra15 gra14 gra13 gra12 gra11 gra10 gra9 gra8 gra7 gra6 gra5 gra4 gra3 gra2 gra1 gra0 grb grb15 grb14 grb13 grb12 grb11 grb10 grb9 grb8 grb7 grb6 grb5 grb4 grb3 grb2 grb1 grb0 grc grc15 grc14 grc13 grc12 grc11 grc10 grc9 grc8 grc7 grc6 grc5 grc4 grc3 grc2 grc1 grc0 grd grd15 grd14 grd13 grd12 grd11 grd10 grd9 grd8 grd7 grd6 grd5 grd4 grd3 grd2 grd1 grd0 flmcr1 ? swe esu psu ev pv e p rom flmcr2 fler ? ? ? ? ? ? ? flpwcr pdwnd ? ? ? ? ? ? ? ebr1 ? ? ? eb4 eb3 eb2 eb1 eb0 fenr flshe ? ? ? ? ? ? ? tcrv0 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 timer v tcsrv cmfb cmfa ovf ? os3 os2 os1 os0 tcora tcora7 tcora6 tcora5 tcora4 tcora3 tcora2 tcora1 tcora0 tcorb tcorb7 tcorb6 tcorb5 tcorb4 tcorb3 tcorb2 tcorb1 tcorb0 tcntv tcntv7 tcntv6 tcntv5 tcntv4 tcntv3 tcntv2 tcntv1 tcntv0 tcrv1 ? ? ? tveg1 tveg0 trge ? icks0 tma tma7 tma6 tma5 ? tma3 tma2 tma1 tma0 timer a tca tca7 tca6 tca5 tca4 tca3 tca2 tca1 tca0
section 19 list of registers rev. 6.00 mar. 24, 2006 page 306 of 412 rej09b0142-0600 register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name smr com chr pe pm stop mp cks1 cks0 sci3 brr brr7 brr6 brr5 brr4 brr3 brr2 brr1 brr0 scr3 tie rie te re mpie teie cke1 cke0 tdr tdr7 tdr6 tdr5 tdr4 tdr3 tdr2 tdr1 tdr0 ssr tdre rdrf oer fer per tend mpbr mpbt rdr rdr7 rdr6 rdr5 rdr4 rdr3 rdr2 rdr1 rdr0 addra ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 a/d converter ad1 ad0 ? ? ? ? ? ? addrb ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 ? ? ? ? ? ? addrc ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 ? ? ? ? ? ? addrd ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 ? ? ? ? ? ? adcsr adf adie adst scan cks ch2 ch1 ch0 adcr trge ? ? ? ? ? ? ? tcsrwd b6wi tcwe b4wi tcsrwe b2wi wdon b0wi wrst wdt * 1 tcwd tcwd7 tcwd6 tcwd5 tcwd4 tcwd3 tcwd2 tcwd1 tcwd0 tmwd ? ? ? ? cks3 cks2 cks1 cks0 iccr ice ieic mst trs acke bbsy iric scp iic icsr estp stop irtr aasx al aas adz ackb icdr icdr7 icdr6 icdr5 icdr4 icdr3 icdr2 icdr1 icdr0 sarx svax6 svax5 svax4 svax3 svax2 svax1 svax0 fsx icmr mls wait cks2 cks1 cks0 bc2 bc1 bc0 sar sva6 sva5 sva4 sva3 sva2 sva1 sva0 fs abrkcr rtinte csel1 csel0 acmp2 acmp1 acmp0 dcmp1 dcmp0 address break abrksr abif abie ? ? ? ? ? ? barh barh7 barh6 barh5 barh4 barh3 barh2 barh1 barh0 barl barl7 barl6 barl5 barl4 barl3 barl2 barl1 barl0 bdrh bdrh7 bdrh6 bdrh5 bdrh4 bdrh3 bdrh2 bdrh1 bdrh0 bdrl bdrl7 bdrl6 bdrl5 bdrl4 bdrl3 bdrl2 bdrl1 bdrl0 pucr1 pucr17 pucr16 pucr15 pucr14 ? pucr12 pucr11 pucr10 i/o port pucr5 ? ? pucr55 pucr54 pucr53 pucr52 pucr51 pucr50 pdr1 p17 p16 p15 p14 ? p12 p11 p10 pdr2 ? ? ? ? ? p22 p21 p20 pdr5 p57 * 2 p56 * 2 p55 p54 p53 p52 p51 p50
section 19 list of registers rev. 6.00 mar. 24, 2006 page 307 of 412 rej09b0142-0600 register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name pdr7 ? p76 p75 p74 ? ? ? ? i/o port pdr8 p87 p86 p85 p84 p83 p82 p81 p80 pdrb pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 pmr1 irq3 irq2 irq1 irq0 ? ? txd tmow pmr5 ? ? wkp5 wkp4 wkp3 wkp2 wkp1 wkp0 pcr1 pcr17 pcr16 pcr15 pcr14 ? pcr12 pcr11 pcr10 pcr2 ? ? ? ? ? pcr22 pcr21 pcr20 pcr5 pcr57 * 2 pcr56 * 2 pcr55 pcr54 pcr53 pcr52 pcr51 pcr50 pcr7 ? pcr76 pcr75 pcr74 ? ? ? ? pcr8 pcr87 pcr86 pcr85 pcr84 pcr83 pcr82 pcr81 pcr80 syscr1 ssby sts2 sts1 sts0 nesel ? ? ? power-down syscr2 smsel lson dton ma2 ma1 ma0 sa1 sa0 iegr1 nmieg ? ? ? ieg3 ie g2 ieg1 ieg0 interrupts iegr2 ? ? wpeg5 wpeg4 wpeg3 wpeg2 wpeg1 wpeg0 ienr1 iendt ienta ienwp ? ien3 ien2 ien1 ien0 irr1 irrdt irrta ? ? irri3 irri2 irri1 irri0 iwpr ? ? iwpf5 iwpf4 iwpf3 iwpf2 iwpf1 iwpf0 mstcr1 ? mstiic msts3 mstad ms twd msttw msttv mstta power-down tscr ? ? ? ? ? ? iicrst iicx iic notes: 1 . wdt: watchdog timer 2. this bit is not included in h8/3664n. ? register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name ekr ekr7 ekr6 ekr5 ekr4 ekr3 ekr2 ekr1 ekr0 eeprom
section 19 list of registers rev. 6.00 mar. 24, 2006 page 308 of 412 rej09b0142-0600 19.3 register states in each operating mode register name reset active sleep subactive subsleep standby module tmrw initialized ? ? ? ? ? timer w tcrw initialized ? ? ? ? ? tierw initialized ? ? ? ? ? tsrw initialized ? ? ? ? ? tior0 initialized ? ? ? ? ? tior1 initialized ? ? ? ? ? tcnt initialized ? ? ? ? ? gra initialized ? ? ? ? ? grb initialized ? ? ? ? ? grc initialized ? ? ? ? ? grd initialized ? ? ? ? ? flmcr1 initialized ? ? initialized initialized initialized rom flmcr2 initialized ? ? ? ? ? flpwcr initialized ? ? ? ? ? ebr1 initialized ? ? initialized initialized initialized fenr initialized ? ? ? ? ? tcrv0 initialized ? ? initialized initialized initialized timer v tcsrv initialized ? ? initialized initialized initialized tcora initialized ? ? initialized initialized initialized tcorb initialized ? ? initialized initialized initialized tcntv initialized ? ? initialized initialized initialized tcrv1 initialized ? ? initialized initialized initialized tma initialized ? ? ? ? ? timer a tca initialized ? ? ? ? ? smr initialized ? ? initialized initialized initialized sci3 brr initialized ? ? initialized initialized initialized scr3 initialized ? ? initialized initialized initialized tdr initialized ? ? initialized initialized initialized ssr initialized ? ? initialized initialized initialized rdr initialized ? ? initializ ed initialized initialized
section 19 list of registers rev. 6.00 mar. 24, 2006 page 309 of 412 rej09b0142-0600 register name reset active sleep subactive subsleep standby module addra initialized ? ? initialized in itialized initialized a/d converter addrb initialized ? ? initia lized initialized initialized addrc initialized ? ? initializ ed initialized initialized addrd initialized ? ? initializ ed initialized initialized adcsr initialized ? ? initialized initialized initialized adcr initialized ? ? initializ ed initialized initialized tcsrwd initialized ? ? ? ? ? wdt * tcwd initialized ? ? ? ? ? tmwd initialized ? ? ? ? ? iccr initialized ? ? ? ? ? iic icsr initialized ? ? ? ? ? icdr initialized ? ? ? ? ? sarx initialized ? ? ? ? ? icmr initialized ? ? ? ? ? sar initialized ? ? ? ? ? abrkcr initialized ? ? ? ? ? address break abrksr initialized ? ? ? ? ? barh initialized ? ? ? ? ? barl initialized ? ? ? ? ? bdrh initialized ? ? ? ? ? bdrl initialized ? ? ? ? ? pucr1 initialized ? ? ? ? ? i/o port pucr5 initialized ? ? ? ? ? pdr1 initialized ? ? ? ? ? pdr2 initialized ? ? ? ? ? pdr5 initialized ? ? ? ? ? pdr7 initialized ? ? ? ? ? pdr8 initialized ? ? ? ? ? pdrb initialized ? ? ? ? ? pmr1 initialized ? ? ? ? ? pmr5 initialized ? ? ? ? ?
section 19 list of registers rev. 6.00 mar. 24, 2006 page 310 of 412 rej09b0142-0600 register name reset active sleep subactive subsleep standby module pcr1 initialized ? ? ? ? ? i/o port pcr2 initialized ? ? ? ? ? pcr5 initialized ? ? ? ? ? pcr7 initialized ? ? ? ? ? pcr8 initialized ? ? ? ? ? syscr1 initialized ? ? ? ? ? power-down syscr2 initialized ? ? ? ? ? power-down iegr1 initialized ? ? ? ? ? interrupts iegr2 initialized ? ? ? ? ? interrupts ienr1 initialized ? ? ? ? ? interrupts irr1 initialized ? ? ? ? ? interrupts iwpr initialized ? ? ? ? ? interrupts mstcr1 initialized ? ? ? ? ? power-down tscr initialized ? ? ? ? ? iic note : ? is not initialized * wdt: watchdog timer ? register name reset active sleep subactive subsleep standby module ekr initialized ? ? ? ? ? eeprom
section 20 electric al characteristics rev. 6.00 mar. 24, 2006 page 311 of 412 rej09b0142-0600 section 20 electrical characteristics 20.1 absolute maximum ratings table 20.1 absolute maximum ratings item symbol value unit note power supply voltage v cc ?0.3 to +7.0 v * analog power supply voltage av cc ?0.3 to +7.0 v input voltage ports other than port b and x1 v in ?0.3 to v cc +0.3 v port b ?0.3 to av cc +0.3 v x1 ?0.3 to 4.3 v operating temperature t opr ?20 to +75 c storage temperature t stg ?55 to +125 c note: * permanent damage may result if maximu m ratings are exceeded. normal operation should be under the conditions specified in electrical characteristics. exceeding these values can result in incorrect operation and reduced reliability. 20.2 electrical characteristics (f -ztat? version, f-ztat? version with eeprom) 20.2.1 power supply voltage and operating ranges power supply voltage and os cillation frequency range 10.0 2.0 16.0 3.0 4.0 5.5 v cc (v) osc (mhz) 32.768 3.0 4.0 5.5 v cc (v) w (khz) av cc = 3.3 v to 5.5 v active mode sleep mode av cc = 3.3 v to 5.5 v all operating modes
section 20 electric al characteristics rev. 6.00 mar. 24, 2006 page 312 of 412 rej09b0142-0600 power supply voltage and op erating frequency range 10.0 1.0 16.0 3.0 4.0 5.5 v cc (v) (mhz) 16.384 3.0 4.0 5.5 v cc (v) sub (khz) 8.192 4.096 1250 78.125 2000 3.0 4.0 5.5 v cc (v) (khz) av cc = 3.3 v to 5.5 v active mode sleep mode (when ma2 = 0 in syscr2) av cc = 3.3 v to 5.5 v subactive mode subsleep mode av cc = 3.3 v to 5.5 v active mode sleep mode (when ma2 = 1 in syscr2)
section 20 electric al characteristics rev. 6.00 mar. 24, 2006 page 313 of 412 rej09b0142-0600 analog power supply voltage and a/d converter accuracy guarantee range 10.0 2.0 16.0 3.3 4.0 5.5 av cc (v) (mhz) v cc = 3.0 v to 5.5 v active mode sleep mode
section 20 electric al characteristics rev. 6.00 mar. 24, 2006 page 314 of 412 rej09b0142-0600 20.2.2 dc characteristics table 20.2 dc characteristics (1) v cc = 3.0 v to 5.5 v, v ss = 0.0 v, t a = ?20c to +75c unless otherwise indicated. values item symbol applicable pins test condition min typ max unit notes input high voltage v ih res , nmi , wkp0 to wkp5 , irq0 to irq3 , adtrg , tmriv, v cc = 4.0 v to 5.5 v v cc 0.8 ? v cc + 0.3 v tmciv, ftci, ftioa to ftiod, sck3, trgv v cc 0.9 ? v cc + 0.3 rxd, scl, sda, p10 to p12, p14 to p17, p20 to p22, v cc = 4.0 v to 5.5 v v cc 0.7 ? v cc + 0.3 v p50 to p57 * , p74 to p76, p80 to p87 v cc 0.8 ? v cc + 0.3 pb0 to pb7 v cc = 4.0 v to 5.5 v v cc 0.7 ? av cc + 0.3 v v cc 0.8 ? av cc + 0.3 osc1 v cc = 4.0 v to 5.5 v v cc ? 0.5 ? v cc + 0.3 v v cc ? 0.3 ? v cc + 0.3 input low voltage v il res , nmi , wkp0 to wkp5 , irq0 to irq3 , adtrg , tmriv, v cc = 4.0 v to 5.5 v ?0.3 ? v cc 0.2 v tmciv, ftci, ftioa to ftiod, sck3, trgv ?0.3 ? v cc 0.1 rxd, scl, sda, p10 to p12, p14 to p17, p20 to p22, v cc = 4.0 v to 5.5 v ?0.3 ? v cc 0.3 v p50 to p57 * , p74 to p76, p80 to p87, pb0 to pb7 ?0.3 ? v cc 0.2 osc1 v cc = 4.0 v to 5.5 v ?0.3 ? 0.5 v ?0.3 ? 0.3 note: * p50 to p55 for h8/3664n
section 20 electric al characteristics rev. 6.00 mar. 24, 2006 page 315 of 412 rej09b0142-0600 values item symbol applicable pins test condition min typ max unit notes output high voltage v oh v cc = 4.0 v to 5.5 v ?i oh = 1.5 ma v cc ? 1.0 ? ? v p10 to p12, p14 to p17, p20 to p22, p50 to p55, p74 to p76, p80 to p87, ?i oh = 0.1 ma v cc ? 0.5 ? ? p56, p57 * v cc = 4.0 v to 5.5 v ?i oh = 0.1 ma v cc ? 2.5 ? ? v v cc = 3.0 v to 4.0 v ?i oh = 0.1 ma v cc ? 2.0 ? ? output low voltage v ol v cc = 4.0 v to 5.5 v i ol = 1.6 ma ? ? 0.6 v p10 to p12, p14 to p17, p20 to p22, p50 to p57 * , p74 to p76, i ol = 0.4 ma ? ? 0.4 p80 to p87 v cc = 4.0 v to 5.5 v i ol = 20.0 ma ? ? 1.5 v v cc = 4.0 v to 5.5 v i ol = 10.0 ma ? ? 1.0 v cc = 4.0 v to 5.5 v i ol = 1.6 ma ? ? 0.4 i ol = 0.4 ma ? ? 0.4 scl, sda v cc = 4.0 v to 5.5 v i ol = 6.0 ma ? ? 0.6 v i ol = 3.0 ma ? ? 0.4 note: * p50 to p55 for h8/3664n
section 20 electric al characteristics rev. 6.00 mar. 24, 2006 page 316 of 412 rej09b0142-0600 values item symbol applicable pins test condition min typ max unit notes input/ output leakage current | i il | osc1, res , nmi , wkp0 to wkp5 , irq0 to irq3 , adtrg , trgv, tmriv, tmciv, ftci, ftioa to ftiod, rxd, sck3, scl, sda v in = 0.5 v to (v cc ? 0.5 v) ? ? 1.0 a p10 to p12, p14 to p17, p20 to p22, p50 to p57 * 1 , p74 to p76, p80 to p87, v in = 0.5 v to (v cc ? 0.5 v) ? ? 1.0 a pb0 to pb7 v in = 0.5 v to (av cc ? 0.5 v) ? ? 1.0 a ?i p v cc = 5.0 v, v in = 0.0 v 50.0 ? 300.0 a pull-up mos current p10 to p12, p14 to p17, p50 to p55 v cc = 3.0 v, v in = 0.0 v ? 60.0 ? reference value input capaci- tance c in all input pins except power supply pins f = 1 mhz, v in = 0.0 v, t a = 25c ? ? 15.0 pf h8/3664n scl, sda ? ? 25.0 i ope1 v cc active mode 1 v cc = 5.0 v, f osc = 16 mhz ? 15.0 22.5 ma * 2 active mode supply current active mode 1 v cc = 3.0 v, f osc = 10 mhz ? 8.0 ? * 2 reference value i ope2 v cc active mode 2 v cc = 5.0 v, f osc = 16 mhz ? 1.8 2.7 ma * 2 active mode 2 v cc = 3.0 v, f osc = 10 mhz ? 1.2 ? * 2 reference value notes: 1. p50 to p55 for h8/3664n 2. pin states during supply current measurem ent are given below (excluding current in the pull-up mos transistors and output buffers).
section 20 electric al characteristics rev. 6.00 mar. 24, 2006 page 317 of 412 rej09b0142-0600 values item symbol applicable pins test condition min typ max unit notes i sleep1 v cc sleep mode 1 v cc = 5.0 v, f osc = 16 mhz ? 11.5 17.0 ma * sleep mode supply current sleep mode 1 v cc = 3.0 v, f osc = 10 mhz ? 6.5 ? * reference value i sleep2 v cc sleep mode 2 v cc = 5.0 v, f osc = 16 mhz ? 1.7 2.5 ma * sleep mode 2 v cc = 3.0 v, f osc = 10 mhz ? 1.1 ? * reference value i sub v cc v cc = 3.0 v 32-khz crystal resonator ( sub = w /2) ? 35.0 70.0 a * subactive mode supply current v cc = 3.0 v 32-khz crystal resonator ( sub = w /8) ? 25.0 ? * reference value subsleep mode supply current i subsp v cc v cc = 3.0 v 32-khz crystal resonator ( sub = w /2) ? 25.0 50.0 a * standby mode supply current i stby v cc 32-khz crystal resonator not used ? ? 5.0 a * ram data retaining voltage v ram v cc 2.0 ? ? v note: * pin states during supply current measurement are given below (excluding current in the pull-up mos transistors and output buffers).
section 20 electric al characteristics rev. 6.00 mar. 24, 2006 page 318 of 412 rej09b0142-0600 mode res pin internal state other pins oscillator pins active mode 1 v cc operates v cc active mode 2 operates ( osc/64) sleep mode 1 v cc only timers operate v cc sleep mode 2 only timers operate ( osc/64) main clock: ceramic or crystal resonator subclock: pin x1 = v ss subactive mode v cc operates v cc subsleep mode v cc only timers operate v cc main clock: ceramic or crystal resonator subclock: crystal resonator standby mode v cc cpu and timers both stop v cc main clock: ceramic or crystal resonator subclock: pin x1 = v ss table 20.2 dc characteristics (2) v cc = 3.0 v to 5.5 v, v ss = 0.0 v, t a = ?20c to +75c, unless otherwise indicated. values item symbol applicable pins test condition min typ max unit notes i eew v cc v cc = 5.0 v, t scl = 2.5 s (when writing) ? ? 2.0 ma * i eer v cc v cc = 5.0 v, t scl = 2.5 s (when reading) ? ? 0.3 ma eeprom supply current i eestby v cc v cc = 5.0 v, t scl = 2.5 s (at standby) ? ? 3.0 a note: * the supply current of t he eeprom chip is shown. for the supply current of h8/3664n, add the above current values to the supply current of h8/3664f.
section 20 electric al characteristics rev. 6.00 mar. 24, 2006 page 319 of 412 rej09b0142-0600 table 20.2 dc characteristics (3) v cc = 3.0 v to 5.5 v, v ss = 0.0 v, t a = ?20c to +75c, unless otherwise indicated. applicable values item symbol pins test condition min typ max unit allowable output low current (per pin) i ol output pins except port 8, scl, and sda v cc = 4.0 v to 5.5 v ? ? 2.0 ma port 8 ? ? 20.0 ma port 8 ? ? 10.0 ma scl and sda ? ? 6.0 ma output pins except port 8, scl, and sda ? ? 0.5 ma allowable output low current (total) i ol output pins except port 8, scl, and sda v cc = 4.0 v to 5.5 v ? ? 40.0 ma port 8, scl, and sda ? ? 80.0 ma output pins except port 8, scl, and sda ? ? 20.0 ma port 8, scl, and sda ? ? 40.0 ma i ?i oh i all output pins v cc = 4.0 v to 5.5 v ? ? 2.0 ma allowable output high current (per pin) ? ? 0.2 ma i ? i oh i all output pins v cc = 4.0 v to 5.5 v ? ? 30.0 ma allowable output high current (total) ? ? 8.0 ma
section 20 electric al characteristics rev. 6.00 mar. 24, 2006 page 320 of 412 rej09b0142-0600 20.2.3 ac characteristics table 20.3 ac characteristics v cc = 3.0 v to 5.5 v, v ss = 0.0 v, t a = ?20c to +75c, unless otherwise specified. values item symbol applicable pins test condition min typ max unit reference figure f osc osc1, osc2 v cc = 4.0 v to 5.5 v 2.0 ? 16.0 mhz * 1 system clock oscillation frequency 2.0 ? 10.0 mhz t cyc 1 ? 64 t osc * 2 system clock ( ) cycle time ? ? 12.8 s subclock oscillation frequency f w x1, x2 ? 32.768 ? khz watch clock ( w ) cycle time t w x1, x2 ? 30.5 ? s subclock ( sub ) cycle time t subcyc 2 ? 8 t w * 2 instruction cycle time 2 ? ? t cyc t subcyc oscillation stabilization time (crystal resonator) t rc osc1, osc2 ? ? 10.0 ms oscillation stabilization time (ceramic resonator) t rc osc1, osc2 ? ? 5.0 ms oscillation stabilization time t rcx x1, x2 ? ? 2.0 s t cph osc1 v cc = 4.0 v to 5.5 v 25.0 ? ? ns figure 20.1 external clock high width 40.0 ? ? t cpl osc1 v cc = 4.0 v to 5.5 v 25.0 ? ? ns external clock low width 40.0 ? ? external clock t cpr osc1 v cc = 4.0 v to 5.5 v ? ? 10.0 ns rise time ? ? 15.0 t cpf osc1 v cc = 4.0 v to 5.5 v ? ? 10.0 ns external clock fall time ? ? 15.0
section 20 electric al characteristics rev. 6.00 mar. 24, 2006 page 321 of 412 rej09b0142-0600 applicable values reference item symbol pins test condition min typ max unit figure res pin low width t rel res at power-on and in modes other than those below t rc ? ? ms figure 20.2 in active mode and sleep mode operation 10 ? ? t cyc input pin high width t ih nmi , irq0 to irq3 , wkp0 to wkp5 , tmciv, tmriv, trgv, adtrg , ftci, ftioa to ftiod 2 ? ? t cyc t subcyc figure 20.3 input pin low width t il nmi , irq0 to irq3 , wkp0 to wkp5 , tmciv, tmriv, trgv, adtrg , ftci, ftioa to ftiod 2 ? ? t cyc t subcyc notes: 1. when an external clock is input, t he minimum system clock oscillator frequency is 1.0 mhz. 2. determined by ma2, ma1, ma0, sa1, and sa0 of system control register 2 (syscr2).
section 20 electric al characteristics rev. 6.00 mar. 24, 2006 page 322 of 412 rej09b0142-0600 table 20.4 i 2 c bus interface timing v cc = 3.0 v to 5.5 v, v ss = 0.0 v, t a = ?20 to +75c, unless otherwise specified. test values reference item symbol condition min typ max unit figure scl input cycle time t scl 12t cyc + 600 ? ? ns figure 20.4 scl input high width t sclh 3t cyc + 300 ? ? ns scl input low width t scll 5t cyc + 300 ? ? ns input fall time of scl and sda t sf ? ? 300 ns scl and sda input spike pulse removal time t sp ? ? 1t cyc ns sda input bus-free time t buf 5t cyc ? ? ns start condition input hold time t stah 3t cyc ? ? ns retransmission start condition input setup time t stas 3t cyc ? ? ns setup time for stop condition input t stos 3t cyc ? ? ns data-input setup time t sdas 1t cyc +20 ? ? ns data-input hold time t sdah 0 ? ? ns capacitive load of scl and sda c b 0 ? 400 pf scl and sda output fall time t sf v cc = 4.0 v to 5.5 v ? ? 250 ns ? ? 300
section 20 electric al characteristics rev. 6.00 mar. 24, 2006 page 323 of 412 rej09b0142-0600 table 20.5 serial int erface (sci3) timing v cc = 3.0 v to 5.5 v, v ss = 0.0 v, t a = ?20c to +75c, unless otherwise specified. applicable values reference item symbol pins test condition min typ max unit figure asynchro- nous t scyc sck3 4 ? ? t cyc figure 20.5 input clock cycle clocked synchro- nous 6 ? ? t cyc input clock pulse width t sckw sck3 0.4 ? 0.6 t scyc t txd txd v cc = 4.0 v to 5.5 v ? ? 1 t cyc figure 20.6 transmit data delay time (clocked synchronous) ? ? 1 t cyc t rxs rxd v cc = 4.0 v to 5.5 v 62.5 ? ? ns receive data setup time (clocked synchronous) 100.0 ? ? ns t rxh rxd v cc = 4.0 v to 5.5 v 62.5 ? ? ns receive data hold time (clocked synchronous) 100.0 ? ? ns
section 20 electric al characteristics rev. 6.00 mar. 24, 2006 page 324 of 412 rej09b0142-0600 20.2.4 a/d converter characteristics table 20.6 a/d convert er characteristics v cc = 3.0 v to 5.5 v, v ss = 0.0 v, t a = ?20c to +75c, unless otherwise specified. applicable test values reference item symbol pins condition min typ max unit figure analog power supply voltage av cc av cc 3.3 v cc 5.5 v * 1 analog input voltage av in an0 to an7 v ss ? 0.3 ? av cc + 0.3 v analog power supply current ai ope av cc av cc = 5.0 v f osc = 16 mhz ? ? 2.0 ma ai stop1 av cc ? 50 ? a * 2 reference value ai stop2 av cc ? ? 5.0 a * 3 analog input capacitance c ain an0 to an7 ? ? 30.0 pf allowable signal source impedance r ain an0 to an7 ? ? 5.0 k ? resolution (data length) 10 10 10 bit conversion time (single mode) av cc = 3.3 v to 5.5 v 134 ? ? t cyc nonlinearity error ? ? 7.5 lsb offset error ? ? 7.5 lsb full-scale error ? ? 7.5 lsb quantization error ? ? 0.5 lsb absolute accuracy ? ? 8.0 lsb conversion time (single mode) av cc = 4.0 v to 5.5 v 70 ? ? t cyc nonlinearity error ? ? 7.5 lsb offset error ? ? 7.5 lsb full-scale error ? ? 7.5 lsb quantization error ? ? 0.5 lsb absolute accuracy ? ? 8.0 lsb
section 20 electric al characteristics rev. 6.00 mar. 24, 2006 page 325 of 412 rej09b0142-0600 applicable test values reference item symbol pins condition min typ max unit figure conversion time (single mode) av cc = 4.0 v to 5.5 v 134 ? ? t cyc nonlinearity error ? ? 3.5 lsb offset error ? ? 3.5 lsb full-scale error ? ? 3.5 lsb quantization error ? ? 0.5 lsb absolute accuracy ? ? 4.0 lsb notes: 1. set av cc = v cc when the a/d converter is not used. 2. ai stop1 is the current in active and sleep m odes while the a/d converter is idle. 3. ai stop2 is the current at reset and in standby, subactive, and subsleep modes while the a/d converter is idle. 20.2.5 watchdog timer characteristics table 20.7 watchdog ti mer characteristics v cc = 3.0 v to 5.5 v, v ss = 0.0 v, t a = ?20c to +75c, unless otherwise specified. applicable values reference item symbol pins test condition min typ max unit figure on-chip oscillator overflow time t ovf 0.2 0.4 ? s * note: * shows the time to count from 0 to 255, at which point an internal reset is generated, when the internal oscillator is selected.
section 20 electric al characteristics rev. 6.00 mar. 24, 2006 page 326 of 412 rej09b0142-0600 20.2.6 memory characteristics table 20.8 flash memory characteristics v cc = 3.0 v to 5.5 v, v ss = 0.0 v, t a = ?20c to +75c, unless otherwise specified. test values item symbol condition min typ max unit programming time (per 128 bytes) * 1 * 2 * 4 t p ? 7 200 ms erase time (per block) * 1 * 3 * 6 t e ? 100 1200 ms reprogramming count n wec 1000 10000 ? times programming wait time after swe bit setting * 1 x 1 ? ? s wait time after psu bit setting * 1 y 50 ? ? s wait time after p bit setting * 1 * 4 z1 1 n 6 28 30 32 s z2 7 n 1000 198 200 202 s z3 additional- programming 8 10 12 s wait time after p bit clear * 1 5 ? ? s wait time after psu bit clear * 1 5 ? ? s wait time after pv bit setting * 1 4 ? ? s wait time after dummy write * 1 2 ? ? s wait time after pv bit clear * 1 2 ? ? s wait time after swe bit clear * 1 100 ? ? s maximum programming count * 1 * 4 * 5 n ? ? 1000 times
section 20 electric al characteristics rev. 6.00 mar. 24, 2006 page 327 of 412 rej09b0142-0600 test values item symbol condition min typ max unit erase wait time after swe bit setting * 1 x 1 ? ? s wait time after esu bit setting * 1 y 100 ? ? s wait time after e bit setting * 1 * 6 z 10 ? 100 ms wait time after e bit clear * 1 10 ? ? s wait time after esu bit clear * 1 10 ? ? s wait time after ev bit setting * 1 20 ? ? s wait time after dummy write * 1 2 ? ? s wait time after ev bit clear * 1 4 ? ? s wait time after swe bit clear * 1 100 ? ? s maximum erase count * 1 * 6 * 7 n ? ? 120 times notes: 1. make the time se ttings in accordance with the program/erase algorithms. 2. the programming time for 128 bytes. (indicate s the total time for which the p bit in flash memory control register 1 (flmcr1) is set. the program-verify time is not included.) 3. the time required to erase one block. (i ndicates the time for which the e bit in flash memory control register 1 (flmcr1) is set. the erase-verify time is not included.) 4. programming time maximum value (t p (max)) = wait time after p bit setting (z) maximum programming count (n) 5. set the maximum programming count (n) acco rding to the actual se t values of z1, z2, and z3, so that it does not exceed the programming time maximum value (t p (max)). the wait time after p bit setting (z1, z2) s hould be changed as follows according to the value of the programming count (n). programming count (n) 1 n 6 z1 = 30 s 7 n 1000 z2 = 200 s 6. erase time maximum value (t e (max)) = wait time after e bit setting (z) maximum erase count (n) 7. set the maximum maximum erase count (n) a ccording to the actual set value of (z), so that it does not exceed the erase time maximum value (t e (max)).
section 20 electric al characteristics rev. 6.00 mar. 24, 2006 page 328 of 412 rej09b0142-0600 20.2.7 eeprom characteristics table 20.9 eeprom characteristics v cc = 3.0 v to 5.5 v, v ss = 0.0 v, t a = ?20c to +75c, unless otherwise specified. test values reference item symbol condition min typ max unit figure scl input cycle time t scl 2500 ? ns figure 20.7 scl input high pulse width t sclh 600 ? ? s scl input low pulse width t scll 1200 ? ? ns scl, sda input spike pulse removal time t sp ? ? 50 ns sda input bus-free time t buf 1200 ? ? ns start condition input hold time t stah 600 ? ? ns retransmit start condition input setup time t stas 600 ? ? ns stop condition input setup time t stos 600 ? ? ns data input setup time t sdas 160 ? ? ns data input hold time t sdah 0 ? ? ns scl, sda input fall time t sf ? ? 300 ns sda input rise time t sr ? ? 300 ns data output hold time t dh 50 ? ? ns scl, sda capacitive load c b 0 ? 400 pf access time t aa 100 ? 900 ns cycle time at writing * t wc ? ? 10 ms reset release time t res ? ? 13 ms note: * cycle time at writing is a time from t he stop condition to write completion (internal control).
section 20 electric al characteristics rev. 6.00 mar. 24, 2006 page 329 of 412 rej09b0142-0600 20.3 electrical characteristics (mask rom version) 20.3.1 power supply voltage and operating ranges power supply voltage and os cillation frequency range 10.0 2.0 16.0 2.7 4.0 5.5 v cc (v) osc (mhz) 32.768 2.7 4.0 5.5 v cc (v) w (khz) av cc = 3.0 v to 5.5 v active mode sleep mode av cc = 3.0 v to 5.5 v all operating modes
section 20 electric al characteristics rev. 6.00 mar. 24, 2006 page 330 of 412 rej09b0142-0600 power supply voltage and op erating frequency range 10.0 1.0 16.0 2.7 4.0 5.5 v cc (v) (mhz) 16.384 2.7 4.0 5.5 v cc (v) sub (khz) 8.192 4.096 1250 78.125 2000 2.7 4.0 5.5 v cc (v) (khz) av cc = 3.0 v to 5.5 v active mode sleep mode (when ma2 = 0 in syscr2) av cc = 3.0 v to 5.5 v subactive mode subsleep mode av cc = 3.0 v to 5.5 v active mode sleep mode (when ma2 = 1 in syscr2)
section 20 electric al characteristics rev. 6.00 mar. 24, 2006 page 331 of 412 rej09b0142-0600 analog power supply voltage and a/d co nverter accuracy guarantee range: 10.0 2.0 16.0 3.0 4.0 5.5 av cc (v) (mhz) v cc = 2.7 v to 5.5 v active mode sleep mode 20.3.2 dc characteristics table 20.10 dc characteristics (1) v cc = 2.7 v to 5.5 v, v ss = 0.0 v, t a = ?20c to +75c unless otherwise indicated. values item symbol applicable pins test condition min typ max unit notes input high voltage v ih res , nmi , wkp0 to wkp5 , irq0 to irq3 , adtrg , tmriv, v cc = 4.0 v to 5.5 v v cc 0.8 ? v cc + 0.3 v tmciv, ftci, ftioa to ftiod, sck3, trgv v cc 0.9 ? v cc + 0.3 v rxd, scl, sda, p10 to p12, p14 to p17, p20 to p22, v cc = 4.0 v to 5.5 v v cc 0.7 ? v cc + 0.3 v p50 to p57, p74 to p76, p80 to p87 v cc 0.8 ? v cc + 0.3 v pb0 to pb7 v cc = 4.0 v to 5.5 v v cc 0.7 ? av cc + 0.3 v v cc 0.8 ? av cc + 0.3 v osc1 v cc = 4.0 v to 5.5 v v cc ? 0.5 ? v cc + 0.3 v v cc ? 0.3 ? v cc + 0.3 v
section 20 electric al characteristics rev. 6.00 mar. 24, 2006 page 332 of 412 rej09b0142-0600 values item symbol applicable pins test condition min typ max unit notes input low voltage v il res , nmi , wkp0 to wkp5 , irq0 to irq3 , adtrg , tmriv, v cc = 4.0 v to 5.5 v ?0.3 ? v cc 0.2 v tmciv, ftci, ftioa to ftiod, sck3, trgv ?0.3 ? v cc 0.1 v rxd, scl, sda, p10 to p12, p14 to p17, p20 to p22, v cc = 4.0 v to 5.5 v ?0.3 ? v cc 0.3 v p50 to p57, p74 to p76, p80 to p87, pb0 to pb7 ?0.3 ? v cc 0.2 v osc1 v cc = 4.0 v to 5.5 v ?0.3 ? 0.5 v ?0.3 ? 0.3 v output high voltage v oh v cc = 4.0 v to 5.5 v ?i oh = 1.5 ma v cc ? 1.0 ? ? v p10 to p12, p14 to p17, p20 to p22, p50 to p55, p74 to p76, p80 to p87 ?i oh = 0.1 ma v cc ? 0.5 ? ? v p56, p57 v cc = 4.0 v to 5.5 v ?i oh = 0.1 ma v cc ? 2.5 ? ? v v cc =2.7 v to 4.0 v ?i oh = 0.1 ma v cc ? 2.0 ? ? v
section 20 electric al characteristics rev. 6.00 mar. 24, 2006 page 333 of 412 rej09b0142-0600 values item symbol applicable pins test condition min typ max unit notes output low voltage v ol v cc = 4.0 v to 5.5 v i ol = 1.6 ma ? ? 0.6 v p10 to p12, p14 to p17, p20 to p22, p50 to p57, p74 to p76 i ol = 0.4 ma ? ? 0.4 v p80 to p87 v cc = 4.0 v to 5.5 v i ol = 20.0 ma ? ? 1.5 v v cc = 4.0 v to 5.5 v i ol = 10.0 ma ? ? 1.0 v v cc = 4.0 v to 5.5 v i ol = 1.6 ma ? ? 0.4 v i ol = 0.4 ma ? ? 0.4 v scl, sda v cc = 4.0 to i ol = 6.0 ma ? ? 0.6 v i ol = 3.0 ma ? ? 0.4 v input/ output leakage current | i il | osc1, res , nmi , wkp0 to wkp5 , irq0 to irq3 , adtrg , trgv, tmriv, tmciv, ftci, ftioa to ftiod, rxd, sck3, scl, sda v in = 0.5 v to (v cc ? 0.5 v) ? ? 1.0 a p10 to p12, p14 to p17, p20 to p22, p50 to p57, p74 to p76, p80 to p87 v in = 0.5 v to (v cc ? 0.5 v) ? ? 1.0 a pb0 to pb7 v in = 0.5 v to (av cc ? 0.5 v) ? ? 1.0 a ?i p p10 to p12, p14 to p17, v cc = 5.0 v, v in = 0.0 v 50.0 ? 300.0 a pull-up mos current p50 to p55 v cc = 3.0 v, v in = 0.0 v ? 60.0 ? a reference value
section 20 electric al characteristics rev. 6.00 mar. 24, 2006 page 334 of 412 rej09b0142-0600 values item symbol applicable pins test condition min typ max unit notes input capaci- tance c in all input pins except power supply pins f = 1 mhz, v in = 0.0 v, t a = 25c ? ? 15.0 pf i ope1 v cc active mode 1 v cc = 5.0 v, f osc = 16 mhz ? 15.0 22.5 ma * active mode supply current active mode 1 v cc = 3.0 v, f osc = 10 mhz ? 8.0 ? ma * reference value i ope2 v cc active mode 2 v cc = 5.0 v, f osc = 16 mhz ? 1.8 2.7 ma * active mode 2 v cc = 3.0 v, f osc = 10 mhz ? 1.2 ? ma * reference value i sleep1 v cc sleep mode 1 v cc = 5.0 v, f osc = 16 mhz ? 7.1 13.0 ma * sleep mode supply current sleep mode 1 v cc = 3.0 v, f osc = 10 mhz ? 4.0 ? ma * reference value i sleep2 v cc sleep mode 2 v cc = 5.0 v, f osc = 16 mhz ? 1.1 2.0 ma * sleep mode 2 v cc = 3.0 v, f osc = 10 mhz ? 0.5 ? ma * reference value i sub v cc v cc = 3.0 v 32-khz crystal resonator ( sub = w /2) ? 35.0 70.0 a * subactive mode supply current v cc = 3.0 v 32-khz crystal resonator ( sub = w /8) ? 25.0 ? a * reference value subsleep mode supply current i subsp v cc v cc = 3.0 v 32-khz crystal resonator ( sub = w /2) ? 25.0 50.0 a * standby mode supply current i stby v cc 32-khz crystal resonator not used ? ? 5.0 a *
section 20 electric al characteristics rev. 6.00 mar. 24, 2006 page 335 of 412 rej09b0142-0600 values item symbol applicable pins test condition min typ max unit notes ram data retaining voltage v ram v cc 2.0 ? ? v note: * pin states during supply current measurement are given below (excluding current in the pull-up mos transistors and output buffers). mode res pin internal state other pins oscillator pins active mode 1 v cc operates v cc active mode 2 operates ( osc/64) sleep mode 1 v cc only timers operate v cc sleep mode 2 only timers operate ( osc/64) main clock: ceramic or crystal resonator subclock: pin x 1 = v ss subactive mode v cc operates v cc main clock: ceramic or crystal resonator subsleep mode v cc only timers operate v cc subclock: crystal resonator standby mode v cc cpu and timers both stop v cc main clock: ceramic or crystal resonator subclock: pin x 1 = v ss
section 20 electric al characteristics rev. 6.00 mar. 24, 2006 page 336 of 412 rej09b0142-0600 table 20.10 dc characteristics (2) v cc = 2.7 v to 5.5 v, v ss = 0.0 v, t a = ?20c to +75c, unless otherwise indicated. applicable values item symbol pins test condition min typ max unit allowable output low current (per pin) i ol output pins except port 8, scl, and sda v cc = 4.0 v to 5.5 v ? ? 2.0 ma port 8 ? ? 20.0 ma port 8 ? ? 10.0 ma scl and sda ? ? 6.0 ma output pins except port 8, scl,, and sda ? ? 0.5 ma allowable output low current (total) i ol output pins except port 8, scl and sda v cc = 4.0 v to 5.5 v ? ? 40.0 ma port 8, scl, and sda ? ? 80.0 ma output pins except port 8, scl, and sda ? ? 20.0 ma port 8, scl, and sda ? ? 40.0 ma i ?i oh i all output pins v cc = 4.0 v to 5.5 v ? ? 2.0 ma allowable output high current (per pin) ? ? 0.2 ma i ? i oh i all output pins v cc = 4.0 v to 5.5 v ? ? 30.0 ma allowable output high current (total) ? ? 8.0 ma
section 20 electric al characteristics rev. 6.00 mar. 24, 2006 page 337 of 412 rej09b0142-0600 20.3.3 ac characteristics table 20.11 ac characteristics v cc = 2.7 v to 5.5 v, v ss = 0.0 v, t a = ?20c to +75c, unless otherwise specified. applicable values reference item symbol pins test condition min typ max unit figure f osc osc1, osc2 v cc = 4.0 v to 5.5 v 2.0 ? 16.0 mhz * 1 system clock oscillation frequency 2.0 10.0 t cyc 1 ? 64 t osc * 2 system clock ( ) cycle time ? ? 12.8 s subclock oscillation frequency f w x1, x2 ? 32.768 ? khz watch clock ( w ) cycle time t w x1, x2 ? 30.5 ? s subclock ( sub ) cycle time t subcyc 2 ? 8 t w * 2 instruction cycle time 2 ? ? t cyc t subcyc oscillation stabilization time (crystal resonator) t rc osc1, osc2 ? ? 10.0 ms oscillation stabilization time (ceramic resonator) t rc osc1, osc2 ? ? 5.0 ms oscillation stabilization time t rcx x1, x2 ? ? 2.0 s t cph osc1 v cc = 4.0 v to 5.5 v 25.0 ? ? ns figure 20.1 external clock high width 40.0 ? ? ns t cpl osc1 v cc = 4.0 v to 5.5 v 25.0 ? ? ns external clock low width 40.0 ? ? ns t cpr osc1 v cc = 4.0 v to 5.5 v ? ? 10.0 ns external clock rise time ? ? 15.0 ns t cpf osc1 v cc = 4.0 v to 5.5 v ? ? 10.0 ns external clock fall time ? ? 15.0 ns
section 20 electric al characteristics rev. 6.00 mar. 24, 2006 page 338 of 412 rej09b0142-0600 applicable values reference item symbol pins test condition min typ max unit figure res pin low width t rel res at power-on and in modes other than those below t rc ? ? ms figure 20.2 in active mode and sleep mode operation 10 ? ? t cyc input pin high width t ih nmi , irq0 to irq3 , wkp0 to wkp5 , tmciv, tmriv, trgv, adtrg , ftci, ftioa to ftiod 2 ? ? t cyc t subcyc figure 20.3 input pin low width t il nmi , irq0 to irq3 , wkp0 to wkp5 , tmciv, tmriv, trgv, adtrg , ftci, ftioa to ftiod 2 ? ? t cyc t subcyc notes: 1. when an external clock is input, t he minimum system clock oscillator frequency is 1.0 mhz. 2. determined by ma2, ma1, ma0, sa1, and sa0 of system control register 2 (syscr2).
section 20 electric al characteristics rev. 6.00 mar. 24, 2006 page 339 of 412 rej09b0142-0600 table 20.12 i 2 c bus interface timing values test reference item symbol min typ max unit condition figure scl input cycle time t scl 12t cyc + 600 ? ? ns figure 20.4 scl input high width t sclh 3t cyc + 300 ? ? ns scl input low width t scll 5t cyc + 300 ? ? ns input fall time of scl and sda t sf ? ? 300 ns scl and sda input spike pulse removal time t sp ? ? 1t cyc ns sda input bus-free time t buf 5t cyc ? ? ns start condition input hold time t stah 3t cyc ? ? ns retransmission start condition input setup time t stas 3t cyc ? ? ns setup time for stop condition input t stos 3t cyc ? ? ns data-input setup time t sdas 1t cyc +20 ? ? ns data-input hold time t sdah 0 ? ? ns capacitive load of scl and sda c b 0 ? 400 pf scl and sda output fall time t sf ? ? 250 ns v cc = 4.0 v to 5.5 v ? ? 300 ns
section 20 electric al characteristics rev. 6.00 mar. 24, 2006 page 340 of 412 rej09b0142-0600 table 20.13 serial int erface (sci3) timing v cc = 2.7 v to 5.5 v, v ss = 0.0 v, t a = ?20c to +75c, unless otherwise specified. applicable values reference item symbol pins test condition min typ max unit figure input clock asynchro- nous t scyc sck3 4 ? ? t cyc figure 20.5 cycle clocked synchronous 6 ? ? t cyc input clock pulse width t sckw sck3 0.4 ? 0.6 t scyc t txd txd v cc = 4.0 v to 5.5 v ? ? 1 t cyc figure 20.6 transmit data delay time (clocked synchronous) ? ? 1 t cyc t rxs rxd v cc = 4.0 v to 5.5 v 62.5 ? ? ns receive data setup time (clocked synchronous) 100.0 ? ? ns t rxh rxd v cc = 4.0 v to 5.5 v 62.5 ? ? ns receive data hold time (clocked synchronous) 100.0 ? ? ns
section 20 electric al characteristics rev. 6.00 mar. 24, 2006 page 341 of 412 rej09b0142-0600 20.3.4 a/d converter characteristics table 20.14 a/d converter characteristics v cc = 2.7 v to 5.5 v, v ss = 0.0 v, t a = ?20c to +75c, unless otherwise specified. applicable test values reference item symbol pins condition min typ max unit figure analog power supply voltage av cc av cc 3.0 v cc 5.5 v * 1 analog input voltage av in an0 to an7 v ss ? 0.3 ? av cc + 0.3 v analog power supply current ai ope av cc av cc = 5.0 v f osc = 16 mhz ? ? 2.0 ma ai stop1 av cc ? 50 ? a * 2 reference value ai stop2 av cc ? ? 5.0 a * 3 analog input capacitance c ain an0 to an7 ? ? 30.0 pf allowable signal source impedance r ain an0 to an7 ? ? 5.0 k ? resolution (data length) 10 10 10 bit conversion time (single mode) av cc = 3.0 v to 5.5 v 134 ? ? t cyc nonlinearity error ? ? 7.5 lsb offset error ? ? 7.5 lsb full-scale error ? ? 7.5 lsb quantization error ? ? 0.5 lsb absolute accuracy ? ? 8.0 lsb conversion time (single mode) av cc = 4.0 v to 5.5 v 70 ? ? t cyc nonlinearity error ? ? 7.5 lsb offset error ? ? 7.5 lsb full-scale error ? ? 7.5 lsb quantization error ? ? 0.5 lsb absolute accuracy ? ? 8.0 lsb
section 20 electric al characteristics rev. 6.00 mar. 24, 2006 page 342 of 412 rej09b0142-0600 applicable test values reference item symbol pins condition min typ max unit figure conversion time (single mode) av cc = 4.0 v to 5.5 v 134 ? ? t cyc nonlinearity error ? ? 3.5 lsb offset error ? ? 3.5 lsb full-scale error ? ? 3.5 lsb quantization error ? ? 0.5 lsb absolute accuracy ? ? 4.0 lsb notes: 1. set av cc = v cc when the a/d converter is not used. 2. ai stop1 is the current in active and sleep m odes while the a/d converter is idle. 3. ai stop2 is the current at reset and in standby, subactive, and subsleep modes while the a/d converter is idle. 20.3.5 watchdog timer characteristics table 20.15 watchdog timer characteristics v cc = 2.7 v to 5.5 v, v ss = 0.0 v, t a = ?20c to +75c, unless otherwise specified. applicable test values reference item symbol pins condition min typ max unit figure on-chip oscillator overflow time t ovf 0.2 0.4 ? s * note: * shows the time to count from 0 to 255, at which point an internal reset is generated, when the internal oscillator is selected.
section 20 electric al characteristics rev. 6.00 mar. 24, 2006 page 343 of 412 rej09b0142-0600 20.4 operation timing t osc v ih v il t cph t cpl t cpr osc1 t cpf figure 20.1 system clock input timing t rel v il res t rel v il v cc 0.7 v cc osc1 figure 20.2 res low width timing v ih v il t il nmi irq0 to irq3 wkp0 to wkp5 adtrg tmci ftioa to ftiod tmciv, tmriv trgv t ih figure 20.3 input timing
section 20 electric al characteristics rev. 6.00 mar. 24, 2006 page 344 of 412 rej09b0142-0600 scl v ih v il t stah t buf p * s * t sf t scl t sdah t sclh t scll sda sr * t stas t sp t stos t sdas p * note: * s, p, and sr represent the following: s: start condition p: stop condition sr: retransmission start condition figure 20.4 i 2 c bus interface input/output timing t scyc t sckw sck3 figure 20.5 sck3 input clock timing
section 20 electric al characteristics rev. 6.00 mar. 24, 2006 page 345 of 412 rej09b0142-0600 t scyc t txd t rxs t rxh v oh v or v ih oh v or v il ol * * * v ol * sck3 txd (transmit data) rxd (receive data) note: * output timing reference levels output high: v oh = 2.0 v output low: v ol = 0.8 v load conditions are shown in figure 20.8. figure 20.6 sci3 input/output timing in clocked synchronous mode scl sda (in) sda (out) t sf t sp t sr t stas t sdah t stos t sclh t scll 1/f scl t buf t sdas t stah t aa t dh figure 20.7 eeprom bus timing
section 20 electric al characteristics rev. 6.00 mar. 24, 2006 page 346 of 412 rej09b0142-0600 20.5 output load condition v cc 2.4 k ? 12 k ? 30 pf lsi output pin figure 20.8 output load circuit
appendix rev. 6.00 mar. 24, 2006 page 347 of 412 rej09b0142-0600 appendix a instruction set a.1 instruction list operand notation symbol description rd general (destination * ) register rs general (source * ) register rn general register * erd general destination register (address register or 32-bit register) ers general source register (addr ess register or 32-bit register) ern general register (32-bit register) (ead) destination operand (eas) source operand pc program counter sp stack pointer ccr condition-code register n n (negative) flag in ccr z z (zero) flag in ccr v v (overflow) flag in ccr c c (carry) flag in ccr disp displacement transfer from the operand on the left to the operand on the right, or transition from the state on the left to the state on the right + addition of the operands on both sides ? subtraction of the op erand on the right from the operand on the left multiplication of the operands on both sides division of the operand on the left by the operand on the right logical and of the operands on both sides logical or of the operands on both sides
appendix rev. 6.00 mar. 24, 2006 page 348 of 412 rej09b0142-0600 symbol description logical exclusive or of the operands on both sides ? not (logical complement) ( ), < > contents of operand note: general registers include 8-bit registers (r0h to r7h and r0l to r7l) and 16-bit registers (r0 to r7 and e0 to e7). condition code notation symbol description ? changed according to execution result * undetermined (no guaranteed value) 0 cleared to 0 1 set to 1 ? not affected by execution of the instruction ? varies depending on conditions, described in notes
appendix rev. 6.00 mar. 24, 2006 page 349 of 412 rej09b0142-0600 table a.1 instruction set 1. data transfer instructions mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? mov.b #xx:8, rd mov.b rs, rd mov.b @ers, rd mov.b @(d:16, ers), rd mov.b @(d:24, ers), rd mov.b @ers+, rd mov.b @aa:8, rd mov.b @aa:16, rd mov.b @aa:24, rd mov.b rs, @erd mov.b rs, @(d:16, erd) mov.b rs, @(d:24, erd) mov.b rs, @?erd mov.b rs, @aa:8 mov.b rs, @aa:16 mov.b rs, @aa:24 mov.w #xx:16, rd mov.w rs, rd mov.w @ers, rd mov.w @(d:16, ers), rd mov.w @(d:24, ers), rd mov.w @ers+, rd mov.w @aa:16, rd mov.w @aa:24, rd mov.w rs, @erd mov.w rs, @(d:16, erd) mov.w rs, @(d:24, erd) operation #xx:8 rd8 rs8 rd8 @ers rd8 @(d:16, ers) rd8 @(d:24, ers) rd8 @ers rd8 ers32+1 ers32 @aa:8 rd8 @aa:16 rd8 @aa:24 rd8 rs8 @erd rs8 @(d:16, erd) rs8 @(d:24, erd) erd32?1 erd32 rs8 @erd rs8 @aa:8 rs8 @aa:16 rs8 @aa:24 #xx:16 rd16 rs16 rd16 @ers rd16 @(d:16, ers) rd16 @(d:24, ers) rd16 @ers rd16 ers32+2 @erd32 @aa:16 rd16 @aa:24 rd16 rs16 @erd rs16 @(d:16, erd) rs16 @(d:24, erd) b b b b b b b b b b b b b b b b w w w w w w w w w w w 2 4 2 2 2 2 2 2 4 8 4 8 4 8 4 8 2 2 2 2 4 6 2 4 6 4 6 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 4 6 10 6 4 6 8 4 6 10 6 4 6 8 4 2 4 6 10 6 6 8 4 6 10 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? mov
appendix rev. 6.00 mar. 24, 2006 page 350 of 412 rej09b0142-0600 mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? mov.w rs, @?erd mov.w rs, @aa:16 mov.w rs, @aa:24 mov.l #xx:32, rd mov.l ers, erd mov.l @ers, erd mov.l @(d:16, ers), erd mov.l @(d:24, ers), erd mov.l @ers+, erd mov.l @aa:16, erd mov.l @aa:24, erd mov.l ers, @erd mov.l ers, @(d:16, erd) mov.l ers, @(d:24, erd) mov.l ers, @?erd mov.l ers, @aa:16 mov.l ers, @aa:24 pop.w rn pop.l ern push.w rn push.l ern movfpe @aa:16, rd movtpe rs, @aa:16 operation erd32?2 erd32 rs16 @erd rs16 @aa:16 rs16 @aa:24 #xx:32 rd32 ers32 erd32 @ers erd32 @(d:16, ers) erd32 @(d:24, ers) erd32 @ers erd32 ers32+4 ers32 @aa:16 erd32 @aa:24 erd32 ers32 @erd ers32 @(d:16, erd) ers32 @(d:24, erd) erd32?4 erd32 ers32 @erd ers32 @aa:16 ers32 @aa:24 @sp rn16 sp+2 sp @sp ern32 sp+4 sp sp?2 sp rn16 @sp sp?4 sp ern32 @sp cannot be used in this lsi cannot be used in this lsi w w w l l l l l l l l l l l l l l w l w l b b 6 2 4 4 6 10 6 10 2 4 4 4 6 6 8 6 8 4 4 2 4 2 4 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 6 8 6 2 8 10 14 10 10 12 8 10 14 10 10 12 6 10 6 10 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? cannot be used in this lsi cannot be used in this lsi mov pop push movfpe movtpe
appendix rev. 6.00 mar. 24, 2006 page 351 of 412 rej09b0142-0600 2. arithmetic instructions mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? add.b #xx:8, rd add.b rs, rd add.w #xx:16, rd add.w rs, rd add.l #xx:32, erd add.l ers, erd addx.b #xx:8, rd addx.b rs, rd adds.l #1, erd adds.l #2, erd adds.l #4, erd inc.b rd inc.w #1, rd inc.w #2, rd inc.l #1, erd inc.l #2, erd daa rd sub.b rs, rd sub.w #xx:16, rd sub.w rs, rd sub.l #xx:32, erd sub.l ers, erd subx.b #xx:8, rd subx.b rs, rd subs.l #1, erd subs.l #2, erd subs.l #4, erd dec.b rd dec.w #1, rd dec.w #2, rd operation rd8+#xx:8 rd8 rd8+rs8 rd8 rd16+#xx:16 rd16 rd16+rs16 rd16 erd32+#xx:32 erd32 erd32+ers32 erd32 rd8+#xx:8 +c rd8 rd8+rs8 +c rd8 erd32+1 erd32 erd32+2 erd32 erd32+4 erd32 rd8+1 rd8 rd16+1 rd16 rd16+2 rd16 erd32+1 erd32 erd32+2 erd32 rd8 decimal adjust rd8 rd8?rs8 rd8 rd16?#xx:16 rd16 rd16?rs16 rd16 erd32?#xx:32 erd32 erd32?ers32 erd32 rd8?#xx:8?c rd8 rd8?rs8?c rd8 erd32?1 erd32 erd32?2 erd32 erd32?4 erd32 rd8?1 rd8 rd16?1 rd16 rd16?2 rd16 b b w w l l b b l l l b w w l l b b w w l l b b l l l b w w 2 4 6 2 4 6 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (1) (1) (2) (2) ? ? ? ? ? ? ? ? * (1) (1) (2) (2) ? ? ? ? ? ? 2 2 4 2 6 2 2 2 2 2 2 2 2 2 2 2 2 2 4 2 6 2 2 2 2 2 2 2 2 2 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (3) (3) ? ? ? (3) (3) ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? * ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? add addx adds inc daa sub subx subs dec
appendix rev. 6.00 mar. 24, 2006 page 352 of 412 rej09b0142-0600 mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? dec.l #1, erd dec.l #2, erd das.rd mulxu. b rs, rd mulxu. w rs, erd mulxs. b rs, rd mulxs. w rs, erd divxu. b rs, rd divxu. w rs, erd divxs. b rs, rd divxs. w rs, erd cmp.b #xx:8, rd cmp.b rs, rd cmp.w #xx:16, rd cmp.w rs, rd cmp.l #xx:32, erd cmp.l ers, erd operation erd32?1 erd32 erd32?2 erd32 rd8 decimal adjust rd8 rd8 rs8 rd16 (unsigned multiplication) rd16 rs16 erd32 (unsigned multiplication) rd8 rs8 rd16 (signed multiplication) rd16 rs16 erd32 (signed multiplication) rd16 rs8 rd16 (rdh: remainder, rdl: quotient) (unsigned division) erd32 rs16 erd32 (ed: remainder, rd: quotient) (unsigned division) rd16 rs8 rd16 (rdh: remainder, rdl: quotient) (signed division) erd32 rs16 erd32 (ed: remainder, rd: quotient) (signed division) rd8?#xx:8 rd8?rs8 rd16?#xx:16 rd16?rs16 erd32?#xx:32 erd32?ers32 l l b b w b w b w b w b b w w l l 2 4 6 2 2 2 2 2 4 4 2 2 4 4 2 2 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2 2 2 14 22 16 24 14 22 16 24 2 2 4 2 4 2 normal advanced ? ? ? ? ? * ? ? ? ? ? ? ? ? (1) (1) (2) (2) ? ? ? ? ? * ? ? ? ? ? ? ? ? ? ? (7) (7) (7) (7) ? ? (6) (6) (8) (8) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? dec das mulxu mulxs divxu divxs cmp
appendix rev. 6.00 mar. 24, 2006 page 353 of 412 rej09b0142-0600 mnemonic operation operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? neg.b rd neg.w rd neg.l erd extu.w rd extu.l erd exts.w rd exts.l erd 0?rd8 rd8 0?rd16 rd16 0?erd32 erd32 0 ( of rd16) 0 ( of erd32) ( of rd16) ( of rd16) ( of erd32) ( of erd32) b w l w l w l 2 2 2 2 2 2 2 ? ? ? ? ? ? ? ? ? ? ? 2 2 2 2 2 2 2 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 ? ? ? ? ? ? ? ? ? ? neg extu exts
appendix rev. 6.00 mar. 24, 2006 page 354 of 412 rej09b0142-0600 3. logic instructions mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? and.b #xx:8, rd and.b rs, rd and.w #xx:16, rd and.w rs, rd and.l #xx:32, erd and.l ers, erd or.b #xx:8, rd or.b rs, rd or.w #xx:16, rd or.w rs, rd or.l #xx:32, erd or.l ers, erd xor.b #xx:8, rd xor.b rs, rd xor.w #xx:16, rd xor.w rs, rd xor.l #xx:32, erd xor.l ers, erd not.b rd not.w rd not.l erd operation rd8 #xx:8 rd8 rd8 rs8 rd8 rd16 #xx:16 rd16 rd16 rs16 rd16 erd32 #xx:32 erd32 erd32 ers32 erd32 rd8 ? #xx:8 rd8 rd8 ? rs8 rd8 rd16 ? #xx:16 rd16 rd16 ? rs16 rd16 erd32 ? #xx:32 erd32 erd32 ? ers32 erd32 rd8 #xx:8 rd8 rd8 rs8 rd8 rd16 #xx:16 rd16 rd16 rs16 rd16 erd32 #xx:32 erd32 erd32 ers32 erd32 ? rd8 rd8 ? rd16 rd16 ? rd32 rd32 b b w w l l b b w w l l b b w w l l b w l 2 4 6 2 4 6 2 4 6 2 2 4 2 2 4 2 2 4 2 2 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 4 2 6 4 2 2 4 2 6 4 2 2 4 2 6 4 2 2 2 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? and or xor not
appendix rev. 6.00 mar. 24, 2006 page 355 of 412 rej09b0142-0600 4. shift instructions mnemonic operand size no. of states * 1 condition code ihnzvc shal.b rd shal.w rd shal.l erd shar.b rd shar.w rd shar.l erd shll.b rd shll.w rd shll.l erd shlr.b rd shlr.w rd shlr.l erd rotxl.b rd rotxl.w rd rotxl.l erd rotxr.b rd rotxr.w rd rotxr.l erd rotl.b rd rotl.w rd rotl.l erd rotr.b rd rotr.w rd rotr.l erd b w l b w l b w l b w l b w l b w l b w l b w l ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 normal advanced ? ? ? ? addressing mode and instruction length (bytes) #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 operation msb lsb 0 c msb lsb 0 c c msb lsb 0c msb lsb c msb lsb c msb lsb c msb lsb c msb lsb ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? shal shar shll shlr rotxl rotxr rotl rotr
appendix rev. 6.00 mar. 24, 2006 page 356 of 412 rej09b0142-0600 5. bit manipulation instructions mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? bset #xx:3, rd bset #xx:3, @erd bset #xx:3, @aa:8 bset rn, rd bset rn, @erd bset rn, @aa:8 bclr #xx:3, rd bclr #xx:3, @erd bclr #xx:3, @aa:8 bclr rn, rd bclr rn, @erd bclr rn, @aa:8 bnot #xx:3, rd bnot #xx:3, @erd bnot #xx:3, @aa:8 bnot rn, rd bnot rn, @erd bnot rn, @aa:8 btst #xx:3, rd btst #xx:3, @erd btst #xx:3, @aa:8 btst rn, rd btst rn, @erd btst rn, @aa:8 bld #xx:3, rd operation (#xx:3 of rd8) 1 (#xx:3 of @erd) 1 (#xx:3 of @aa:8) 1 (rn8 of rd8) 1 (rn8 of @erd) 1 (rn8 of @aa:8) 1 (#xx:3 of rd8) 0 (#xx:3 of @erd) 0 (#xx:3 of @aa:8) 0 (rn8 of rd8) 0 (rn8 of @erd) 0 (rn8 of @aa:8) 0 (#xx:3 of rd8) ? (#xx:3 of rd8) (#xx:3 of @erd) ? (#xx:3 of @erd) (#xx:3 of @aa:8) ? (#xx:3 of @aa:8) (rn8 of rd8) ? (rn8 of rd8) (rn8 of @erd) ? (rn8 of @erd) (rn8 of @aa:8) ? (rn8 of @aa:8) ? (#xx:3 of rd8) z ? (#xx:3 of @erd) z ? (#xx:3 of @aa:8) z ? (rn8 of @rd8) z ? (rn8 of @erd) z ? (rn8 of @aa:8) z (#xx:3 of rd8) c b b b b b b b b b b b b b b b b b b b b b b b b b 2 2 2 2 2 2 2 2 2 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2 8 8 2 8 8 2 8 8 2 8 8 2 8 8 2 8 8 2 6 6 2 6 6 2 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bset bclr bnot btst bld
appendix rev. 6.00 mar. 24, 2006 page 357 of 412 rej09b0142-0600 mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? bld #xx:3, @erd bld #xx:3, @aa:8 bild #xx:3, rd bild #xx:3, @erd bild #xx:3, @aa:8 bst #xx:3, rd bst #xx:3, @erd bst #xx:3, @aa:8 bist #xx:3, rd bist #xx:3, @erd bist #xx:3, @aa:8 band #xx:3, rd band #xx:3, @erd band #xx:3, @aa:8 biand #xx:3, rd biand #xx:3, @erd biand #xx:3, @aa:8 bor #xx:3, rd bor #xx:3, @erd bor #xx:3, @aa:8 bior #xx:3, rd bior #xx:3, @erd bior #xx:3, @aa:8 bxor #xx:3, rd bxor #xx:3, @erd bxor #xx:3, @aa:8 bixor #xx:3, rd bixor #xx:3, @erd bixor #xx:3, @aa:8 operation (#xx:3 of @erd) c (#xx:3 of @aa:8) c ? (#xx:3 of rd8) c ? (#xx:3 of @erd) c ? (#xx:3 of @aa:8) c c (#xx:3 of rd8) c (#xx:3 of @erd24) c (#xx:3 of @aa:8) ? c (#xx:3 of rd8) ? c (#xx:3 of @erd24) ? c (#xx:3 of @aa:8) c (#xx:3 of rd8) c c (#xx:3 of @erd24) c c (#xx:3 of @aa:8) c c ? (#xx:3 of rd8) c c ? (#xx:3 of @erd24) c c ? (#xx:3 of @aa:8) c c (#xx:3 of rd8) c c (#xx:3 of @erd24) c c (#xx:3 of @aa:8) c c ? (#xx:3 of rd8) c c ? (#xx:3 of @erd24) c c ? (#xx:3 of @aa:8) c c (#xx:3 of rd8) c c (#xx:3 of @erd24) c c (#xx:3 of @aa:8) c c ? (#xx:3 of rd8) c c ? (#xx:3 of @erd24) c c ? (#xx:3 of @aa:8) c b b b b b b b b b b b b b b b b b b b b b b b b b b b b b 2 2 2 2 2 2 2 2 2 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 6 6 2 6 6 2 8 8 2 8 8 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bld bild bist bst band biand bor bior bxor bixor
appendix rev. 6.00 mar. 24, 2006 page 358 of 412 rej09b0142-0600 6. branching instructions ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? mnemonic operand size no. of states * 1 condition code ihnzvc bra d:8 (bt d:8) bra d:16 (bt d:16) brn d:8 (bf d:8) brn d:16 (bf d:16) bhi d:8 bhi d:16 bls d:8 bls d:16 bcc d:8 (bhs d:8) bcc d:16 (bhs d:16) bcs d:8 (blo d:8) bcs d:16 (blo d:16) bne d:8 bne d:16 beq d:8 beq d:16 bvc d:8 bvc d:16 bvs d:8 bvs d:16 bpl d:8 bpl d:16 bmi d:8 bmi d:16 bge d:8 bge d:16 blt d:8 blt d:16 bgt d:8 bgt d:16 ble d:8 ble d:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 normal advanced addressing mode and instruction length (bytes) #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 operation always never c z = 0 c z = 1 c = 0 c = 1 z = 0 z = 1 v = 0 v = 1 n = 0 n = 1 n v = 0 n v = 1 z (n v) = 0 z (n v) = 1 if condition is true then pc pc+d else next; branch condition bcc
appendix rev. 6.00 mar. 24, 2006 page 359 of 412 rej09b0142-0600 mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? jmp @ern jmp @aa:24 jmp @@aa:8 bsr d:8 bsr d:16 jsr @ern jsr @aa:24 jsr @@aa:8 rts operation pc ern pc aa:24 pc @aa:8 pc @?sp pc pc+d:8 pc @?sp pc pc+d:16 pc @?sp pc ern pc @?sp pc aa:24 pc @?sp pc @aa:8 pc @sp+ ? ? ? ? ? ? ? ? ? 2 2 4 4 2 4 2 2 2 ? ? ? ? ? ? ? ? ? 4 6 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 8 6 8 6 8 8 8 10 8 10 8 10 12 10 jmp bsr jsr rts
appendix rev. 6.00 mar. 24, 2006 page 360 of 412 rej09b0142-0600 7. system control instructions mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? trapa #x:2 rte sleep ldc #xx:8, ccr ldc rs, ccr ldc @ers, ccr ldc @(d:16, ers), ccr ldc @(d:24, ers), ccr ldc @ers+, ccr ldc @aa:16, ccr ldc @aa:24, ccr stc ccr, rd stc ccr, @erd stc ccr, @(d:16, erd) stc ccr, @(d:24, erd) stc ccr, @?erd stc ccr, @aa:16 stc ccr, @aa:24 andc #xx:8, ccr orc #xx:8, ccr xorc #xx:8, ccr nop operation pc @?sp ccr @?sp pc ccr @sp+ pc @sp+ transition to power- down state #xx:8 ccr rs8 ccr @ers ccr @(d:16, ers) ccr @(d:24, ers) ccr @ers ccr ers32+2 ers32 @aa:16 ccr @aa:24 ccr ccr rd8 ccr @erd ccr @(d:16, erd) ccr @(d:24, erd) erd32?2 erd32 ccr @erd ccr @aa:16 ccr @aa:24 ccr #xx:8 ccr ccr #xx:8 ccr ccr #xx:8 ccr pc pc+2 ? ? ? b b w w w w w w b w w w w w w b b b ? 2 2 2 2 2 2 4 4 6 10 6 10 4 4 6 8 6 8 2 2 1 ? ? ? ? ? ? ? ? ? 10 2 2 2 6 8 12 8 8 10 2 6 8 12 8 8 10 2 2 2 2 normal advanced ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 14 16 trapa rte sleep ldc stc andc orc xorc nop
appendix rev. 6.00 mar. 24, 2006 page 361 of 412 rej09b0142-0600 8. block transfer instructions mnemonic operand size addressing mode and instruction length (bytes) no. of states * 1 condition code ihnzvc #xx rn @ern @(d, ern) @?ern/@ern+ @aa @(d, pc) @@aa ? eepmov. b eepmov. w operation if r4l 0 then repeat @r5 @r6 r5+1 r5 r6+1 r6 r4l?1 r4l until r4l=0 else next if r4 0 then repeat @r5 @r6 r5+1 r5 r6+1 r6 r4?1 r4 until r4=0 else next ? ? 4 4 ? ? 8+ 4n * 2 normal advanced ? ? ? ? ? ? ? ? ? ?8+ 4n * 2 eepmov notes: 1. the number of states in cases wher e the instruction code and its operands are located in on-chip memory is shown here. for ot her cases see appendix a.3, number of execution states. 2. n is the value set in register r4l or r4. (1) set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0. (2) set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0. (3) retains its previous value when the result is zero; otherwise cleared to 0. (4) set to 1 when the adjustment produces a carry; otherwise retains its previous value. (5) the number of states required for executi on of an instruction t hat transfers data in synchronization with the e clock is variable. (6) set to 1 when the divisor is negative; otherwise cleared to 0. (7) set to 1 when the divisor is zero; otherwise cleared to 0. (8) set to 1 when the quotient is negative; otherwise cleared to 0.
appendix rev. 6.00 mar. 24, 2006 page 362 of 412 rej09b0142-0600 a.2 operation code map table a.2 operation code map (1) ah al 0123456789abcdef 0 1 2 3 4 5 6 7 8 9 a b c d e f nop bra mulxu bset brn divxu bnot stc bhi mulxu bclr ldc bls divxu btst orc or.b bcc rts or xorc xor.b bcs bsr xor bor bior bxor bixor band biand andc and.b bne rte and ldc beq trapa bld bild bst bist bvc mov bpl jmp bmi eepmov addx subx bgt jsr ble mov add addx cmp subx or xor and mov instruction when most significant bit of bh is 0. instruction when most significant bit of bh is 1. instruction code: table a-2 (2) table a-2 (2) table a-2 (2) table a-2 (2) table a-2 (2) bvs blt bge bsr table a-2 (2) table a-2 (2) table a-2 (2) table a-2 (2) table a-2 (2) table a-2 (2) table a-2 (2) table a-2 (2) table a-2 (2) table a-2 (2) table a-2 (3) 1st byte 2nd byte ah bh al bl add sub mov cmp mov.b
appendix rev. 6.00 mar. 24, 2006 page 363 of 412 rej09b0142-0600 table a.2 operation code map (2) ah al bh 0123456789abcdef 01 0a 0b 0f 10 11 12 13 17 1a 1b 1f 58 79 7a mov inc adds daa dec subs das bra mov mov bhi cmp cmp ldc/stc bcc or or bpl bgt instruction code: bvs sleep bvc bge table a-2 (3) table a-2 (3) table a-2 (3) add mov sub cmp bne and and inc extu dec beq inc extu dec bcs xor xor shll shlr rotxl rotxr not bls sub sub brn add add inc exts dec blt inc exts dec ble shal shar rotl rotr neg bmi 1st byte 2nd byte ah bh al bl sub adds shll shlr rotxl rotxr not shal shar rotl rotr neg
appendix rev. 6.00 mar. 24, 2006 page 364 of 412 rej09b0142-0600 table a.2 operation code map (3) ah albh blch cl 0123456789abcdef 01406 01c05 01d05 01f06 7cr06 7cr07 7dr06 7dr07 7eaa6 7eaa7 7faa6 7faa7 mulxs bset bset bset bset divxs bnot bnot bnot bnot mulxs bclr bclr bclr bclr divxs btst btst btst btst or xor bor bior bxor bixor band biand and bld bild bst bist instruction when most significant bit of dh is 0. instruction when most significant bit of dh is 1. instruction code: * * * * * * * * 1 1 1 1 2 2 2 2 bor bior bxor bixor band biand bld bild bst bist notes: 1. 2. r is the register designation field. aa is the absolute address field. 1st byte 2nd byte ah bh al bl 3rd byte ch dh cl dl 4th byte ldc stc ldc ldc ldc stc stc stc
appendix rev. 6.00 mar. 24, 2006 page 365 of 412 rej09b0142-0600 a.3 number of execution states the status of execution for each instruction of the h8/300h cpu and the method of calculating the number of states required for instructio n execution are shown belo w. table a.4 shows the number of cycles of each type occurring in each instruction, such as in struction fetch and data read/write. table a.3 shows the number of states required for each cycle. the total number of states required for execution of an instruction can be calculated by the following expression: execution states = i s i + j s j + k s k + l s l + m s m + n s n examples: when instruction is fetched from on-chi p rom, and an on-chip ram is accessed. bset #0, @ff00 from table a.4: i = l = 2, j = k = m = n= 0 from table a.3: s i = 2, s l = 2 number of states required for execution = 2 2 + 2 2 = 8 when instruction is fetched from on-chip rom, branch address is read from on-chip rom, and on-chip ram is used for stack area. jsr @@ 30 from table a.4: i = 2, j = k = 1, l = m = n = 0 from table a.3: s i = s j = s k = 2 number of states required for execution = 2 2 + 1 2+ 1 2 = 8
appendix rev. 6.00 mar. 24, 2006 page 366 of 412 rej09b0142-0600 table a.3 number of cycles in each instruction execution status access location (instruction cycle) on-chip me mory on-chip peripheral module instruction fetch s i 2 ? branch address read s j stack operation s k byte data access s l 2 or 3 * word data access s m ? internal operation s n 1 note: * depends on which on-chip peripheral module is accessed. see section 19.1, register addresses (address order).
appendix rev. 6.00 mar. 24, 2006 page 367 of 412 rej09b0142-0600 table a.4 number of cycles in each instruction instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n add add.b #xx:8, rd add.b rs, rd add.w #xx:16, rd add.w rs, rd add.l #xx:32, erd add.l ers, erd 1 1 2 1 3 1 adds adds #1/2/4, erd 1 addx addx #xx:8, rd addx rs, rd 1 1 and and.b #xx:8, rd and.b rs, rd and.w #xx:16, rd and.w rs, rd and.l #xx:32, erd and.l ers, erd 1 1 2 1 3 2 andc andc #xx:8, ccr 1 band band #xx:3, rd band #xx:3, @erd band #xx:3, @aa:8 1 2 2 1 1 bcc bra d:8 (bt d:8) brn d:8 (bf d:8) bhi d:8 bls d:8 bcc d:8 (bhs d:8) bcs d:8 (blo d:8) bne d:8 beq d:8 bvc d:8 bvs d:8 bpl d:8 bmi d:8 bge d:8 2 2 2 2 2 2 2 2 2 2 2 2 2
appendix rev. 6.00 mar. 24, 2006 page 368 of 412 rej09b0142-0600 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n bcc blt d:8 bgt d:8 ble d:8 bra d:16(bt d:16) brn d:16(bf d:16) bhi d:16 bls d:16 bcc d:16(bhs d:16) bcs d:16(blo d:16) bne d:16 beq d:16 bvc d:16 bvs d:16 bpl d:16 bmi d:16 bge d:16 blt d:16 bgt d:16 ble d:16 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 bclr bclr #xx:3, rd bclr #xx:3, @erd bclr #xx:3, @aa:8 bclr rn, rd bclr rn, @erd bclr rn, @aa:8 1 2 2 1 2 2 2 2 2 2 biand biand #xx:3, rd biand #xx:3, @erd biand #xx:3, @aa:8 1 2 2 1 1 bild bild #xx:3, rd bild #xx:3, @erd bild #xx:3, @aa:8 1 2 2 1 1
appendix rev. 6.00 mar. 24, 2006 page 369 of 412 rej09b0142-0600 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n bior bior #xx:8, rd bior #xx:8, @erd bior #xx:8, @aa:8 1 2 2 1 1 bist bist #xx:3, rd bist #xx:3, @erd bist #xx:3, @aa:8 1 2 2 2 2 bixor bixor #xx:3, rd bixor #xx:3, @erd bixor #xx:3, @aa:8 1 2 2 1 1 bld bld #xx:3, rd bld #xx:3, @erd bld #xx:3, @aa:8 1 2 2 1 1 bnot bnot #xx:3, rd bnot #xx:3, @erd bnot #xx:3, @aa:8 bnot rn, rd bnot rn, @erd bnot rn, @aa:8 1 2 2 1 2 2 2 2 2 2 bor bor #xx:3, rd bor #xx:3, @erd bor #xx:3, @aa:8 1 2 2 1 1 bset bset #xx:3, rd bset #xx:3, @erd bset #xx:3, @aa:8 bset rn, rd bset rn, @erd bset rn, @aa:8 1 2 2 1 2 2 2 2 2 2 bsr bsr d:8 bsr d:16 2 2 1 1 2 bst bst #xx:3, rd bst #xx:3, @erd bst #xx:3, @aa:8 1 2 2 2 2
appendix rev. 6.00 mar. 24, 2006 page 370 of 412 rej09b0142-0600 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n btst btst #xx:3, rd btst #xx:3, @erd btst #xx:3, @aa:8 btst rn, rd btst rn, @erd btst rn, @aa:8 1 2 2 1 2 2 1 1 1 1 bxor bxor #xx:3, rd bxor #xx:3, @erd bxor #xx:3, @aa:8 1 2 2 1 1 cmp cmp.b #xx:8, rd cmp.b rs, rd cmp.w #xx:16, rd cmp.w rs, rd cmp.l #xx:32, erd cmp.l ers, erd 1 1 2 1 3 1 daa daa rd 1 das das rd 1 dec dec.b rd dec.w #1/2, rd dec.l #1/2, erd 1 1 1 duvxs divxs.b rs, rd divxs.w rs, erd 2 2 12 20 divxu divxu.b rs, rd divxu.w rs, erd 1 1 12 20 eepmov eepmov.b eepmov.w 2 2 2n+2 * 1 2n+2 * 1 exts exts.w rd exts.l erd 1 1 extu extu.w rd extu.l erd 1 1
appendix rev. 6.00 mar. 24, 2006 page 371 of 412 rej09b0142-0600 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n inc inc.b rd inc.w #1/2, rd inc.l #1/2, erd 1 1 1 jmp jmp @ern jmp @aa:24 jmp @@aa:8 2 2 2 1 2 2 jsr jsr @ern jsr @aa:24 jsr @@aa:8 2 2 2 1 1 1 1 2 ldc ldc #xx:8, ccr ldc rs, ccr ldc@ers, ccr ldc@(d:16, ers), ccr ldc@(d:24,ers), ccr ldc@ers+, ccr ldc@aa:16, ccr ldc@aa:24, ccr 1 1 2 3 5 2 3 4 1 1 1 1 1 1 2 mov mov.b #xx:8, rd mov.b rs, rd mov.b @ers, rd mov.b @(d:16, ers), rd mov.b @(d:24, ers), rd mov.b @ers+, rd mov.b @aa:8, rd mov.b @aa:16, rd mov.b @aa:24, rd mov.b rs, @erd mov.b rs, @(d:16, erd) mov.b rs, @(d:24, erd) mov.b rs, @-erd mov.b rs, @aa:8 1 1 1 2 4 1 1 2 3 1 2 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2
appendix rev. 6.00 mar. 24, 2006 page 372 of 412 rej09b0142-0600 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n mov mov.b rs, @aa:16 mov.b rs, @aa:24 mov.w #xx:16, rd mov.w rs, rd mov.w @ers, rd mov.w @(d:16,ers), rd mov.w @(d:24,ers), rd mov.w @ers+, rd mov.w @aa:16, rd mov.w @aa:24, rd mov.w rs, @erd mov.w rs, @(d:16,erd) mov.w rs, @(d:24,erd) 2 3 2 1 1 2 4 1 2 3 1 2 4 1 1 1 1 1 1 1 1 1 1 1 2 mov mov.w rs, @-erd mov.w rs, @aa:16 mov.w rs, @aa:24 mov.l #xx:32, erd mov.l ers, erd mov.l @ers, erd mov.l @(d:16,ers), erd mov.l @(d:24,ers), erd mov.l @ers+, erd mov.l @aa:16, erd mov.l @aa:24, erd mov.l ers,@erd mov.l ers, @(d:16,erd) mov.l ers, @(d:24,erd) mov.l ers, @-erd mov.l ers, @aa:16 mov.l ers, @aa:24 1 2 3 3 1 2 3 5 2 3 4 2 3 5 2 3 4 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 movfpe movfpe @aa:16, rd * 2 2 1 movtpe movtpe rs,@aa:16 * 2 2 1
appendix rev. 6.00 mar. 24, 2006 page 373 of 412 rej09b0142-0600 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n mulxs mulxs.b rs, rd mulxs.w rs, erd 2 2 12 20 mulxu mulxu.b rs, rd mulxu.w rs, erd 1 1 12 20 neg neg.b rd neg.w rd neg.l erd 1 1 1 nop nop 1 not not.b rd not.w rd not.l erd 1 1 1 or or.b #xx:8, rd or.b rs, rd or.w #xx:16, rd or.w rs, rd or.l #xx:32, erd or.l ers, erd 1 1 2 1 3 2 orc orc #xx:8, ccr 1 pop pop.w rn pop.l ern 1 2 1 2 2 2 push push.w rn push.l ern 1 2 1 2 2 2 rotl rotl.b rd rotl.w rd rotl.l erd 1 1 1 rotr rotr.b rd rotr.w rd rotr.l erd 1 1 1 rotxl rotxl.b rd rotxl.w rd rotxl.l erd 1 1 1
appendix rev. 6.00 mar. 24, 2006 page 374 of 412 rej09b0142-0600 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n rotxr rotxr.b rd rotxr.w rd rotxr.l erd 1 1 1 rte rte 2 2 2 rts rts 2 1 2 shal shal.b rd shal.w rd shal.l erd 1 1 1 shar shar.b rd shar.w rd shar.l erd 1 1 1 shll shll.b rd shll.w rd shll.l erd 1 1 1 shlr shlr.b rd shlr.w rd shlr.l erd 1 1 1 sleep sleep 1 stc stc ccr, rd stc ccr, @erd stc ccr, @(d:16,erd) stc ccr, @(d:24,erd) stc ccr,@-erd stc ccr, @aa:16 stc ccr, @aa:24 1 2 3 5 2 3 4 1 1 1 1 1 1 2 sub sub.b rs, rd sub.w #xx:16, rd sub.w rs, rd sub.l #xx:32, erd sub.l ers, erd 1 2 1 3 1 subs subs #1/2/4, erd 1
appendix rev. 6.00 mar. 24, 2006 page 375 of 412 rej09b0142-0600 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n subx subx #xx:8, rd subx. rs, rd 1 1 trapa trapa #xx:2 2 1 2 4 xor xor.b #xx:8, rd xor.b rs, rd xor.w #xx:16, rd xor.w rs, rd xor.l #xx:32, erd xor.l ers, erd 1 1 2 1 3 2 xorc xorc #xx:8, ccr 1 notes: 1. n:specified value in r4l and r4. the source and destination operands are accessed n+1 times respectively. 2. cannot be used in this lsi.
appendix rev. 6.00 mar. 24, 2006 page 376 of 412 rej09b0142-0600 a.4 combinations of instructions and addressing modes table a.5 combinations of instructions and addressing modes addressing mode mov pop, push movfpe, movtpe add, cmp sub addx, subx adds, subs inc, dec daa, das mulxu, mulxs, divxu, divxs neg extu, exts and, or, xor not bcc, bsr jmp, jsr rts trapa rte sleep ldc stc andc, orc, xorc nop data transfer instructions arithmetic operations logical operations shift operations bit manipulations branching instructions system control instructions block data transfer instructions bwl ? ? bwl wl b ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? b ? b ? ? #xx rn @ern @(d:16.ern) @(d:24.ern) @ern+/@ern @aa:8 @aa:16 @aa:24 @(d:8.pc) @(d:16.pc) @@aa:8 ? bwl ? ? bwl bwl b l bwl b bw bwl wl bwl bwl bwl b ? ? ? ? ? ? b b ? ? ? bwl ? ? ? ? ? ? ? ? ? ? ? ? ? ? b ? ? ? ? ? w w ? ? ? bwl ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? w w ? ? ? bwl ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? w w ? ? ? bwl ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? w w ? ? ? b ? ? ? ? ? ? ? ? ? ? ? ? ? ? b ? ? ? ? ? ? ? ? ? ? ? bwl ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? w w ? ? ? bwl ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? w w ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? wl ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bw functions instructions
appendix rev. 6.00 mar. 24, 2006 page 377 of 412 rej09b0142-0600 appendix b i/o port block diagrams b.1 i/o port block res goes low in a reset, and sby goes low in a reset and in standby mode. [legend] pdr pucr pmr pcr sby res pucr: port pull-up control register pmr: port mode register pdr: port data register pcr: port control register irq trgv internal data bus pull-up mos figure b.1 port 1 block diagram (p17)
appendix rev. 6.00 mar. 24, 2006 page 378 of 412 rej09b0142-0600 [legend] pdr pucr pmr pcr sby res pucr: port pull-up control register pmr: port mode register pdr: port data register pcr: port control register irq internal data bus pull-up mos figure b.2 port 1 block diagram (p16 to p14)
appendix rev. 6.00 mar. 24, 2006 page 379 of 412 rej09b0142-0600 pdr pucr pcr sby res pucr: port pull-up control register pdr: port data register pcr: port control register internal data bus pull-up mos [legend] figure b.3 port 1 block diagram (p12, p11)
appendix rev. 6.00 mar. 24, 2006 page 380 of 412 rej09b0142-0600 [legend] pdr pucr pmr pcr sby res pucr: port pull-up control register pmr: port mode register pdr: port data register pcr: port control register internal data bus tmow timer a pull-up mos figure b.4 port 1 block diagram (p10)
appendix rev. 6.00 mar. 24, 2006 page 381 of 412 rej09b0142-0600 pdr pmr pcr sby pmr: port mode register pdr: port data register pcr: port control register internal data bus txd sci3 [legend] figure b.5 port 2 block diagram (p22)
appendix rev. 6.00 mar. 24, 2006 page 382 of 412 rej09b0142-0600 [legend] pdr pcr sby pdr: port data register pcr: port control register re internal data bus rxd sci3 figure b.6 port 2 block diagram (p21)
appendix rev. 6.00 mar. 24, 2006 page 383 of 412 rej09b0142-0600 pdr pcr sby pdr: port data register pcr: port control register sckie internal data bus scki sci3 sckoe scko [legend] figure b.7 port 2 block diagram (p20)
appendix rev. 6.00 mar. 24, 2006 page 384 of 412 rej09b0142-0600 [legend] pdr pcr sby ice sdao/sclo sdai/scli iic pdr: port data register pcr: port control register internal data bus figure b.8 port 5 block diagram (p57, p56)* note: * not included in h8/3664n.
appendix rev. 6.00 mar. 24, 2006 page 385 of 412 rej09b0142-0600 [legend] pdr pucr pmr pcr sby res pucr: port pull-up control register pmr: port mode register pdr: port data register pcr: port control register wkp internal data bus adtrg pull-up mos figure b.9 port 5 block diagram (p55)
appendix rev. 6.00 mar. 24, 2006 page 386 of 412 rej09b0142-0600 [legend] pdr pucr pmr pcr sby res pucr: port pull-up control register pmr: port mode register pdr: port data register pcr: port control register wkp internal data bus pull-up mos figure b.10 port 5 block diagram (p54 to p50)
appendix rev. 6.00 mar. 24, 2006 page 387 of 412 rej09b0142-0600 pdr pcr sby os3 os2 os1 os0 tmov [legend] pdr: port data register pcr: port control register internal data bus timer v figure b.11 port 7 block diagram (p76)
appendix rev. 6.00 mar. 24, 2006 page 388 of 412 rej09b0142-0600 pdr pcr sby tmciv pdr: port data register pcr: port control register internal data bus timer v [legend] figure b.12 port 7 block diagram (p75)
appendix rev. 6.00 mar. 24, 2006 page 389 of 412 rej09b0142-0600 pdr pcr sby tmriv [legend] pdr: port data register pcr: port control register internal data bus timer v figure b.13 port 7 block diagram (p74)
appendix rev. 6.00 mar. 24, 2006 page 390 of 412 rej09b0142-0600 pdr pcr sby pdr: port data register pcr: port control register internal data bus [legend] figure b.14 port 8 block diagram (p87 to p85)
appendix rev. 6.00 mar. 24, 2006 page 391 of 412 rej09b0142-0600 pdr pcr sby pdr: port data register pcr: port control register internal data bus ftioa ftiob ftioc ftiod timer w output control signals a to d [legend] figure b.15 port 8 block diagram (p84 to p81)
appendix rev. 6.00 mar. 24, 2006 page 392 of 412 rej09b0142-0600 pdr pcr sby ftci pdr: port data register pcr: port control register internal data bus timer w [legend] figure b.16 port 8 block diagram (p80)
appendix rev. 6.00 mar. 24, 2006 page 393 of 412 rej09b0142-0600 dec v in ch3 to ch0 a/d converter internal data bus figure b.17 port b block diagram (pb7 to pb0)
appendix rev. 6.00 mar. 24, 2006 page 394 of 412 rej09b0142-0600 b.2 port states in each operating state port reset sleep subsleep standby subactive active p17 to p14, p12 to p10 high impedance retained retained high impedance * functioning functioning p22 to p20 high impedance retained retained high impedance * functioning functioning p57 to p50 (p55 to p50 for h8/3664n) high impedance retained retained high impedance functioning functioning p76 to p74 high impedance retained retained high impedance functioning functioning p87 to p80 high impedance retained retained high impedance functioning functioning pb7 to pb0 high impedance high impedance high impedance high impedance high impedance high impedance note: * high level output when the pul l-up mos is in on state.
appendix rev. 6.00 mar. 24, 2006 page 395 of 412 rej09b0142-0600 appendix c product code lineup product type product code m odel marking package code h8/3664 flash memory version with eeprom standard product HD64N3664fp HD64N3664fp lqfp-64 (fp-64e) flash memory version standard product hd64f3664fp hd64f3664h hd64f3664fx hd64f3664fy hd64f3664bp hd64f3664fp hd64f3664h hd64f3664fx hd64f3664fy hd64f3664bp lqfp-64 (fp-64e) qfp-64 (fp-64a) lqfp-48 (fp-48f) lqfp-48 (fp-48b) sdip-42 (dp-42s) mask rom version standard product hd6433664fp hd6433664h hd6433664fx hd6433664fy hd6433664bp hd6433664 ( *** ) fp hd6433664 ( *** ) h hd6433664 ( *** ) fx hd6433664 ( *** ) fy hd6433664 ( *** ) bp lqfp-64 (fp-64e) qfp-64 (fp-64a) lqfp-48 (fp-48f) lqfp-48 (fp-48b) sdip-42 (dp-42s) h8/3663 mask rom version standard product hd6433663fp hd6433663h hd6433663fx hd6433663fy hd6433663bp hd6433663 ( *** ) fp hd6433663 ( *** ) h hd6433663 ( *** ) fx hd6433663 ( *** ) fy hd6433663 ( *** ) bp lqfp-64 (fp-64e) qfp-64 (fp-64a) lqfp-48 (fp-48f) lqfp-48 (fp-48b) sdip-42 (dp-42s) h8/3662 mask rom version standard product hd6433662fp hd6433662h hd6433662fx hd6433662fy hd6433662bp hd6433662 ( *** ) fp hd6433662 ( *** ) h hd6433662 ( *** ) fx hd6433662 ( *** ) fy hd6433662 ( *** ) bp lqfp-64 (fp-64e) qfp-64 (fp-64a) lqfp-48 (fp-48f) lqfp-48 (fp-48b) sdip-42 (dp-42s) h8/3661 mask rom version standard product hd6433661fp hd6433661h hd6433661fx hd6433661fy hd6433661bp hd6433661 ( *** ) fp hd6433661 ( *** ) h hd6433661 ( *** ) fx hd6433661 ( *** ) fy hd6433661 ( *** ) bp lqfp-64 (fp-64e) qfp-64 (fp-64a) lqfp-48 (fp-48f) lqfp-48 (fp-48b) sdip-42 (dp-42s)
appendix rev. 6.00 mar. 24, 2006 page 396 of 412 rej09b0142-0600 product type product code m odel marking package code h8/3660 mask rom version standard product hd6433660fp hd6433660h hd6433660fx hd6433660fy hd6433660bp hd6433660 ( *** ) fp hd6433660 ( *** ) h hd6433660 ( *** ) fx hd6433660 ( *** ) fy hd6433660 ( *** ) bp lqfp-64 (fp-64e) qfp-64 (fp-64a) lqfp-48 (fp-48f) lqfp-48 (fp-48b) sdip-42 (dp-42s) [legend] ( *** ): rom code
appendix rev. 6.00 mar. 24, 2006 page 397 of 412 rej09b0142-0600 appendix d package dimensions the package dimensions that are shows in the renesas semiconductor packages data book have priority. package code jedec eiaj mass (reference value) fp-64e ? conforms 0.4 g unit: mm * dimension including the plating thickness base material dimension m 12.0 0.2 10 48 33 116 17 32 64 49 *0.22 0.05 0.08 0.5 12.0 0.2 0.10 1.70 max * 0.17 0.05 0.5 0.2 0 ? 8 1.0 1.45 0.10 0.10 1.25 0.20 0.04 0.15 0.04 figure d.1 fp-64e package dimensions
appendix rev. 6.00 mar. 24, 2006 page 398 of 412 rej09b0142-0600 package code jedec eiaj mass (reference value) fp-64a ? conforms 1.2 g unit: mm * dimension including the plating thickness base material dimension 0.10 0.15 m 17.2 0.3 48 33 49 64 1 16 32 17 17.2 0.3 0.35 0.06 0.8 3.05 max 14 2.70 0 ? 8 1.6 0.8 0.3 * 0.17 0.05 0.10 +0.15 - 0.10 1.0 *0.37 0.08 0.15 0.04 figure d.2 fp-64a package dimensions
appendix rev. 6.00 mar. 24, 2006 page 399 of 412 rej09b0142-0600 package code jedec eiaj mass (reference value) fp-48f ? ? 0.4 g * dimension including the plating thickness base material dimension 0.10 0 ? 8 0.50 0.1 * 0.17 0.05 0.1 0.05 1.65 max 1.0 12.0 0.2 10 * 0.32 0.05 0.13 36 25 112 37 48 24 13 0.65 12.0 0.2 m 0.30 0.04 1.425 1.45 0.15 0.04 unit: mm figure d.3 fp-48f package dimensions
appendix rev. 6.00 mar. 24, 2006 page 400 of 412 rej09b0142-0600 package code jedec jeita mass (reference value) fp-48b ? ? 0.2 g * dimension including the plating thickness base material dimension 9.0 0.2 7 * 0.22 0.05 0.08 36 25 112 37 48 24 13 0.5 9.0 0.2 0.08 1.0 0? ? 8? 0.5 0.1 * 0.17 0.05 1.70 max m 0.75 0.20 0.04 1.40 0.15 0.04 0.10 0.07 unit: mm figure d.4 fp-48b package dimensions package code jedec eiaj mass (reference value) dp-42s ? conforms 4.8 g unit: mm 0.25 + 0.10 - 0.05 0 ? 15 15.24 37.3 38.6 max 1.0 14.0 14.6 max 0.51 min 5.10 max 2.54 min 0.48 0.10 1.78 0.25 42 22 1 21 1.38 max figure d.5 dp-42s package dimensions
appendix rev. 6.00 mar. 24, 2006 page 401 of 412 rej09b0142-0600 appendix e eeprom stacked-structure cross-sectional view figure e.1 eeprom stacked-structure cross-sectional view
appendix rev. 6.00 mar. 24, 2006 page 402 of 412 rej09b0142-0600
rev. 6.00 mar. 24, 2006 page 403 of 412 rej09b0142-0600 main revisions and add itions in this edition item page revision (s ee manual for details) preface notes vi, vii amended when using the on-chip emulator (e7, e8) for h8/3664 program development and debugging, the following restrictions must be noted (the on - chip debugging emulator (e7) can also be used). 1. the nmi pin is reserved for the e7 or e8, and cannot be used. 2. pins p85, p86, and p87 cannot be used. in order to use these pins, additional hardware must be provided on the user board. 3. area h'7000 to h'7fff is used by the e7 or e8, and is not available to the user. 4. area h'f780 to h'fb7f must on no account be accessed. 5. when the e7 or e8 is used, address breaks can be set as either available to the user or for use by the e7 or e8. if address breaks are set as being used by the e7 or e8, the address break control registers must not be accessed. 6. when the e7 or e8 is used, nmi is an input/output pin (open-drain in output mode), p85 and p87 are input pins, and p86 is an output pin. figure 5.3 typical connection to crystal resonator figure 5.5 typical connection to ceramic resonator figure 5.8 typical connection to 32.768-khz crystal resonator 78 to 80 added note: capacitances are reference values.
rev. 6.00 mar. 24, 2006 page 404 of 412 rej09b0142-0600 item page revision (s ee manual for details) 6.1.1 system control register 1 (syscr1) 85 amended bit bit name description 3 nesel noise elimination sampling frequency select the subclock pulse generator generates the watch clock signal ( w ) and the system clock pulse generator generates the oscillator clock ( osc ). this bit selects the sampling frequency of the oscillator clock when the watch clock signal ( w ) is sampled. when osc = 4 to 16 mhz, clear nesel to 0. 0: sampling rate is osc /16 1: sampling rate is osc /4 table 7.2 boot mode operation 102 amended communication contents processing contents host operation lsi operation processing contents continuously transmits data h'00 at specified bit rate. h'00, h'00 . . . h'00 h'00 h'55 h'55 reception. transmits data h'55 when data h'00 is received error-free. item measures low-level period of receive data h'00. calculates bit rate and sets brr in sci3. transmits data h'00 to host as adjustment end indication. bit rate adjustment 9.5.3 pin functions ? p84/ftiod pin 136 amended register tmrw tior1 pcr8 bit name pwmd iod2 iod1 iod0 pcr84 pin function 0 0 0 0 0 p84 input/ftiod input pin 1 p84 output/ftiod input pin 0 0 1 x ftiod output pin 0 1 x x ftiod output pin 1 x x 0 p84 input/ftiod input pin 1 p84 output/ftiod input pin setting value 1 x x x x pwm output pin
rev. 6.00 mar. 24, 2006 page 405 of 412 rej09b0142-0600 item page revision (s ee manual for details) 9.5.3 pin functions ? p83/ftioc pin 136 amended register tmrw tior1 pcr8 bit name pwmc ioc2 ioc1 ioc0 pcr83 pin function 0 0 0 0 0 p83 input/ftioc input pin 1 p83 output/ftioc input pin 0 0 1 x ftioc output pin 0 1 x x ftioc output pin 1 x x 0 p83 input/ftioc input pin 1 p83 output/ftioc input pin setting value 1 x x x x pwm output pin 9.5.3 pin functions ? p82/ftiob pin 137 amended register tmrw tior0 pcr8 bit name pwmb iob2 iob1 iob0 pcr82 pin function 0 0 0 0 0 p82 input/ftiob input pin 1 p82 output/ftiob input pin 0 0 1 x ftiob output pin 0 1 x x ftiob output pin 1 x x 0 p82 input/ftiob input pin 1 p82 output/ftiob input pin setting value 1 x x x x pwm output pin 11.3.4 timer control/status register v (tcsrv) 150, 151 amended bit bit name description 3 2 os3 os2 output select 3 and 2 these bits select an output method for the tmov pin by the compar e match of tcorb and tcntv. 00: no change 01: 0 output1 : 1 0 os1 os0 output select 1 and 0 these bits select an output method for the tmov pin by the compar e match of tcora and tcntv. : 13.2.1 timer control/status register wd (tcsrwd) 192 amended bit bit name description 4 tcsrwe timer control/status register wd write enable :
rev. 6.00 mar. 24, 2006 page 406 of 412 rej09b0142-0600 item page revision (s ee manual for details) 15.5 usage notes ? notes on wait function ? notes on trs bit setting and icdr register access 271 to 274 added. 16.3.1 a/d data registers a to d (addra to addrd) 278 amended ? therefore, byte access to addr should be done by reading the upper byte first then the lower one. word access is also possible. addr is initialized to h'0000. table 20.2 dc characteristics (1) 314 amended values item applicable pins test condition min input high voltage pb0 to pb7 v cc = 4.0 v to 5.5 v v cc 0.7 av cc = 3.3 v to 5.5 v v cc 0.8 input low voltage p50 to p57 * , p74 to p76, p80 to p87, pb0 to pb7 ?0.3 pb0 to pb7 av cc = 4.0 v to 5.5 v ?0.3 av cc = 3.3 v to 5.5 v ?0.3 table 20.2 dc characteristics (1) table 20.10 dc characteristics (1) 318, 335 amended note: * pin states during supply current measurement are given below (excluding current in the pull-up mos transistors and output buffers). mode res pin internal state active mode 1 v cc operates active mode 2 operates ( osc/64) sleep mode 1 v cc only timers operate sleep mode 2 only timers operate ( osc/64)
rev. 6.00 mar. 24, 2006 page 407 of 412 rej09b0142-0600 item page revision (s ee manual for details) table 20.10 dc characteristics (1) 331, 332 amended values item applicable pins test condition min input high voltage pb0 to pb7 v cc = 4.0 v to 5.5 v v cc 0.7 av cc = 3.3 v to 5.5 v v cc 0.8 input low voltage p50 to p57 * , p74 to p76, p80 to p87, pb0 to pb7 ?0.3 pb0 to pb7 av cc = 4.0 v to 5.5 v ?0.3 av cc = 3.3 v to 5.5 v ?0.3 table a.1 instruction set 2. arithmetic instructions 351 amended mnemonic operand size no. of states * 1 condition code ihnzvc daa rd b * 2 normal advanced ? * ? daa ?
rev. 6.00 mar. 24, 2006 page 408 of 412 rej09b0142-0600
rev. 6.00 mar. 24, 2006 page 409 of 412 rej09b0142-0600 index a a/d converter ......................................... 275 sample-and-hold circuit...................... 282 scan mode........................................... 281 single mode ........................................ 281 absolute maximum ratings..................... 311 address break ........................................... 67 addressing modes..................................... 35 absolute address................................... 37 immediate ............................................. 37 memory indirect ................................... 38 program-counter relative ...................... 37 register direct....................................... 36 register indirect.................................... 36 register indirect w ith displacement...... 36 register indirect with post-increment... 36 register indirect with pre-decrement.... 36 c clock clock pulse generators.......................... 77 subclock generator ............................... 80 system clock generator......................... 78 condition-code register (ccr)................. 19 cpu .......................................................... 13 e eeprom................................................ 287 acknowledge ....................................... 291 acknowledge polling.......................... 294 byte write ........................................... 293 corresponding slave address reference address (esar) .................................. 292 current address read ........................... 295 eeprom interface ............................. 290 eeprom key register (ekr) ............. 289 page write ........................................... 293 random address read .......................... 296 sequential read.................................... 296 slave addressing.................................. 292 start cond ition..................................... 291 stop condition ..................................... 291 effective address....................................... 39 electrical characteristics (f-ztat? version, f-ztat? version with eeprom) ac characteristics ............................... 320 electrical characteristics (f-ztat? version, f-ztat? version with eeprom)....................................... 311 dc characteristics ............................... 314 electrical characteristics (mask rom ve rsion) .............................. 329 ac characteristics ............................... 337 dc characteristics ............................... 331 exception handling ................................... 51 reset exception handling ...................... 59 trap instruction..................................... 51 f flash memory on-board progra mming modes ........... 100 flash memory ........................................... 95 boot mode........................................... 101 boot program ...................................... 100 erase/erase-verify ............................... 107 error protection................................... 109 hardware protection............................ 109 power-down st ate................................ 110 program/progra m-verify ..................... 104 programmer mode............................... 110
rev. 6.00 mar. 24, 2006 page 410 of 412 rej09b0142-0600 software prot ection............................. 109 g general registers ....................................... 18 i i/o ports.................................................. 115 i/o port block diagrams ...................... 377 i 2 c bus interface (iic) ............................ 233 acknowledge...................................... 250 clock synchronous serial format ........ 259 general call address............................ 247 i 2 c bus data formats ........................... 250 i 2 c transfer rate................................... 241 slave address ...................................... 250 start cond ition .................................... 250 stop condition..................................... 250 instruction set ........................................... 24 interrupt internal interrupts ................................. 61 interrupt response time ......................... 62 irq3 to irq0 interrupts ....................... 59 nmi interrupt........................................ 59 wkp5 to wkp0 interrupts ................... 60 interrupt mask bit (i)................................. 19 l laminated-structure cross section of h8/3664n ............................................... 401 large current ports...................................... 1 m memory map ............................................ 14 p package....................................................... 2 package dimensions................................ 397 pin arrangement .......................................... 5 power supply circuit internal power supply step-down circuit ............................................................ 299 power supply circuit ............................... 299 power-down modes................................... 83 module standby function ...................... 94 sleep mode............................................ 91 standby mode ....................................... 91 subactive mode..................................... 92 subsleep mode ...................................... 92 prescaler s ................................................ 81 prescaler w ............................................... 81 product code lineup ................................ 395 program counter (pc) ............................... 19 r registers abrkcr...................... 68, 303, 306, 309 abrksr ...................... 70, 303, 306, 309 adcr ......................... 280, 303, 306, 309 adcsr ....................... 279, 303, 306, 309 addra ...................... 278, 303, 306, 309 addrb ...................... 278, 303, 306, 309 addrc ...................... 278, 303, 306, 309 addrd ...................... 278, 303, 306, 309 barh ........................... 70, 303, 306, 309 barl............................ 70, 303, 306, 309 bdrh ........................... 70, 303, 306, 309 bdrl............................ 70, 303, 306, 309 brr ............................ 205, 302, 306, 308 ebr1............................. 99, 302, 305, 308 ekr ............................ 289, 304, 307, 310 fenr .......................... 100, 302, 305, 308 flmcr1....................... 97, 302, 305, 308 flmcr2....................... 98, 302, 305, 308 flpwcr ...................... 99, 302, 305, 308 gra............................ 171, 302, 305, 308
rev. 6.00 mar. 24, 2006 page 411 of 412 rej09b0142-0600 grb............................ 171, 302, 305, 308 grc............................ 171, 302, 305, 308 grd............................ 171, 302, 305, 308 iccr........................... 242, 303, 306, 309 icdr........................... 236, 303, 306, 309 icmr.......................... 239, 303, 306, 309 icsr ........................... 245, 303, 306, 309 iegr1........................... 53, 304, 307, 310 iegr2........................... 54, 304, 307, 310 ienr1........................... 55, 304, 307, 310 irr1 ............................. 56, 304, 307, 310 iwpr ............................ 57, 304, 307, 310 mstcr1....................... 87, 304, 307, 310 pcr1........................... 117, 304, 307, 310 pcr2........................... 121, 304, 307, 310 pcr5........................... 126, 304, 307, 310 pcr7........................... 131, 304, 307, 310 pcr8........................... 134, 304, 307, 310 pdr1 .......................... 118, 303, 306, 309 pdr2 .......................... 122, 303, 306, 309 pdr5 .......................... 127, 303, 306, 309 pdr7 .......................... 131, 303, 307, 309 pdr8 .......................... 134, 303, 307, 309 pdrb.......................... 138, 304, 307, 309 pmr1.......................... 116, 304, 307, 309 pmr5.......................... 125, 304, 307, 309 pucr1........................ 118, 303, 306, 309 pucr5........................ 127, 303, 306, 309 rdr............................ 199, 303, 306, 308 rsr..................................................... 199 sar ............................ 238, 303, 306, 309 sarx ......................... 238, 303, 306, 309 scr3........................... 201, 302, 306, 308 smr............................ 200, 302, 306, 308 ssr ............................. 203, 303, 306, 308 syscr1 ....................... 84, 304, 307, 310 syscr2 ....................... 86, 304, 307, 310 tca ............................ 142, 302, 305, 308 tcnt.......................... 170, 302, 305, 308 tcntv....................... 147, 302, 305, 308 tcora....................... 148, 302, 305, 308 tcorb ....................... 148, 302, 305, 308 tcrv0........................ 148, 302, 305, 308 tcrv1........................ 151, 302, 305, 308 tcrw......................... 164, 302, 305, 308 tcsrv........................ 150, 302, 305, 308 tcsrwd.................... 192, 303, 306, 309 tcwd......................... 193, 303, 306, 309 tdr ............................ 200, 303, 306, 308 tierw........................ 165, 302, 305, 308 tior0 ......................... 167, 302, 305, 308 tior1 ......................... 169, 302, 305, 308 tma............................ 141, 302, 305, 308 tmrw ........................ 163, 302, 305, 308 tmwd........................ 194, 303, 306, 309 tscr .......................... 248, 304, 307, 310 tsr ..................................................... 199 tsrw ......................... 166, 302, 305, 308 s serial communication interface 3 (sci3) 197 asynchronous mode............................ 210 bit rate................................................. 205 break detection ................................... 230 clocked synchronous mode ................ 218 framing error ...................................... 214 mark state ........................................... 231 multiprocessor communication function ............................................... 224 overrun error ...................................... 214 parity error .......................................... 214 stack pointer (sp) ..................................... 19 t timer a................................................... 139 timer v................................................... 145 timer w.................................................. 159 pwm opera tion................................... 176
rev. 6.00 mar. 24, 2006 page 412 of 412 rej09b0142-0600 v vector address .......................................... 52 w watchdog timer....................................... 191
renesas 16-bit single-chip microcomputer hardware manual h8/3664 group publication date: 1st edition, mar, 2000 rev.6.00, mar. 24, 2006 published by: sales strategic planning div. renesas technology corp. edited by: customer support department global strategic communication div. renesas solutions corp. ? 2006. renesas technology corp., all rights reserved. printed in japan.
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h8/3664 group rej09b0142-0600 hardware manual 1753, shimonumabe, nakahara-ku, kawasaki-shi, kanagawa 211-8668 japan

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